Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) * Generic Exynos Bus frequency device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) The Samsung Exynos SoC has many buses for data transfer between DRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) and sub-blocks in SoC. Most Exynos SoCs share the common architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) for buses. Generally, each bus of Exynos SoC includes a source clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) and a power line, which are able to change the clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) of the bus in runtime. To monitor the usage of each bus in runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) the driver uses the PPMU (Platform Performance Monitoring Unit), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) is able to measure the current load of sub-blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) The Exynos SoC includes the various sub-blocks which have the each AXI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) The each AXI bus has the owned source clock but, has not the only owned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) power line. The power line might be shared among one more sub-blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) So, we can divide into two type of device as the role of each sub-block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) There are two type of bus devices as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) - parent bus device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) - passive bus device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) Basically, parent and passive bus device share the same power line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) The parent bus device can only change the voltage of shared power line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) and the rest bus devices (passive bus device) depend on the decision of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) the parent bus device. If there are three blocks which share the VDD_xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) power line, Only one block should be parent device and then the rest blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) should depend on the parent device as passive device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	VDD_xxx |--- A block (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		|--- B block (passive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		|--- C block (passive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) There are a little different composition among Exynos SoC because each Exynos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) SoC has different sub-blocks. Therefore, such difference should be specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) in devicetree file instead of each device driver. In result, this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) is able to support the bus frequency for all Exynos SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) Required properties for all bus devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) - compatible: Should be "samsung,exynos-bus".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) - clock-names : the name of clock used by the bus, "bus".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) - clocks : phandles for clock specified in "clock-names" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) - operating-points-v2: the OPP table including frequency/voltage information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)   to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) Required properties only for parent bus device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) - vdd-supply: the regulator to provide the buses with the voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) - devfreq-events: the devfreq-event device to monitor the current utilization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)   of buses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) Required properties only for passive bus device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) - devfreq: the parent bus device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) Optional properties only for parent bus device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) - exynos,saturation-ratio: the percentage value which is used to calibrate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			the performance count against total cycle count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) Detailed correlation between sub-blocks and power line according to Exynos SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) - In case of Exynos3250, there are two power line as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	VDD_MIF |--- DMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	VDD_INT |--- LEFTBUS (parent device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		|--- PERIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		|--- MFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		|--- G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		|--- RIGHTBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		|--- PERIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		|--- FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		|--- LCD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		|--- PERIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		|--- ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		|--- CAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) - In case of Exynos4210, there is one power line as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	VDD_INT |--- DMC (parent device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		|--- LEFTBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		|--- PERIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		|--- MFC(L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		|--- G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		|--- TV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		|--- LCD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		|--- RIGHTBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		|--- PERIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		|--- MFC(R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		|--- CAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		|--- FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		|--- GPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		|--- LCD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		|--- LCD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) - In case of Exynos4x12, there are two power line as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	VDD_MIF |--- DMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	VDD_INT |--- LEFTBUS (parent device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		|--- PERIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		|--- MFC(L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		|--- G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		|--- TV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		|--- IMAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		|--- RIGHTBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		|--- PERIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		|--- MFC(R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		|--- CAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		|--- FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		|--- GPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		|--- LCD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		|--- ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - In case of Exynos5422, there are two power line as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	        |--- DREX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	VDD_INT |--- NoC_Core (parent device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		|--- G2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		|--- G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		|--- DISP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		|--- NoC_WCORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		|--- GSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		|--- MSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		|--- ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		|--- MFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		|--- GEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		|--- PERIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		|--- PERIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		|--- FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		|--- FSYS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) - In case of Exynos5433, there is VDD_INT power line as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	VDD_INT |--- G2D (parent device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		|--- MSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		|--- GSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		|--- JPEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		|--- MFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		|--- HEVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		|--- BUS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		|--- BUS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		|--- BUS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		|--- PERIS (Fixed clock rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		|--- PERIC (Fixed clock rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		|--- FSYS  (Fixed clock rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Example1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	power line (regulator). The MIF (Memory Interface) AXI bus is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	transfer data between DRAM and CPU and uses the VDD_MIF regulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	- MIF (Memory Interface) block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	: VDD_MIF |--- DMC (Dynamic Memory Controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	- INT (Internal) block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	: VDD_INT |--- LEFTBUS (parent device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		  |--- PERIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		  |--- MFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		  |--- G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		  |--- RIGHTBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		  |--- FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		  |--- LCD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		  |--- PERIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		  |--- ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		  |--- CAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	- MIF bus's frequency/voltage table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	-----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	|Lv| Freq   | Voltage |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	-----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	|L1| 50000  |800000   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	|L2| 100000 |800000   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	|L3| 134000 |800000   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	|L4| 200000 |825000   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	|L5| 400000 |875000   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	-----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	- INT bus's frequency/voltage table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	| name|       |LCD0    |       |       |       ||        |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	|     |       |FSYS    |       |       |       ||        |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	|     |       |MFC     |       |       |       ||        |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	|Mode |*parent|passive |passive|passive|passive||        |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	|Lv   |Frequency                               ||Voltage |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	|L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	|L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	|L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	|L4   |134000 |134000  |200000 |200000 |       ||1000000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	|L5   |200000 |200000  |400000 |300000 |       ||1000000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	----------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) Example2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	is listed below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	bus_dmc: bus_dmc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		clocks = <&cmu_dmc CLK_DIV_DMC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		operating-points-v2 = <&bus_dmc_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bus_dmc_opp_table: opp_table1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		opp-50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			opp-hz = /bits/ 64 <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			opp-microvolt = <800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		opp-100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			opp-hz = /bits/ 64 <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			opp-microvolt = <800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		opp-134000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			opp-hz = /bits/ 64 <134000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			opp-microvolt = <800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		opp-200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			opp-hz = /bits/ 64 <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			opp-microvolt = <825000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		opp-400000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			opp-hz = /bits/ 64 <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			opp-microvolt = <875000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	bus_leftbus: bus_leftbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		clocks = <&cmu CLK_DIV_GDL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		operating-points-v2 = <&bus_leftbus_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	bus_rightbus: bus_rightbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		clocks = <&cmu CLK_DIV_GDR>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		operating-points-v2 = <&bus_leftbus_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	bus_lcd0: bus_lcd0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		clocks = <&cmu CLK_DIV_ACLK_160>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		operating-points-v2 = <&bus_leftbus_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	bus_fsys: bus_fsys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		clocks = <&cmu CLK_DIV_ACLK_200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		operating-points-v2 = <&bus_leftbus_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	bus_mcuisp: bus_mcuisp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		operating-points-v2 = <&bus_mcuisp_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	bus_isp: bus_isp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		clocks = <&cmu CLK_DIV_ACLK_266>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		operating-points-v2 = <&bus_isp_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bus_peril: bus_peril {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		clocks = <&cmu CLK_DIV_ACLK_100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		operating-points-v2 = <&bus_peril_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	bus_mfc: bus_mfc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		compatible = "samsung,exynos-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		clocks = <&cmu CLK_SCLK_MFC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		clock-names = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		operating-points-v2 = <&bus_leftbus_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	bus_leftbus_opp_table: opp_table1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		opp-50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			opp-hz = /bits/ 64 <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			opp-microvolt = <900000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		opp-80000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			opp-hz = /bits/ 64 <80000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			opp-microvolt = <900000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		opp-100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			opp-hz = /bits/ 64 <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			opp-microvolt = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		opp-134000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			opp-hz = /bits/ 64 <134000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			opp-microvolt = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		opp-200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			opp-hz = /bits/ 64 <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			opp-microvolt = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	bus_mcuisp_opp_table: opp_table2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		opp-50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			opp-hz = /bits/ 64 <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		opp-80000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			opp-hz = /bits/ 64 <80000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		opp-100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			opp-hz = /bits/ 64 <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		opp-200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			opp-hz = /bits/ 64 <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		opp-400000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			opp-hz = /bits/ 64 <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	bus_isp_opp_table: opp_table3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		opp-50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			opp-hz = /bits/ 64 <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		opp-80000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			opp-hz = /bits/ 64 <80000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		opp-100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			opp-hz = /bits/ 64 <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		opp-200000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			opp-hz = /bits/ 64 <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		opp-300000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			opp-hz = /bits/ 64 <300000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	bus_peril_opp_table: opp_table4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		opp-50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			opp-hz = /bits/ 64 <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		opp-80000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			opp-hz = /bits/ 64 <80000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		opp-100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			opp-hz = /bits/ 64 <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	Usage case to handle the frequency and voltage of bus on runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	in exynos3250-rinato.dts is listed below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	&bus_dmc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	&bus_leftbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		vdd-supply = <&buck3_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	&bus_rightbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		devfreq = <&bus_leftbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	&bus_lcd0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		devfreq = <&bus_leftbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	&bus_fsys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		devfreq = <&bus_leftbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	&bus_mcuisp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		devfreq = <&bus_leftbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	&bus_isp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		devfreq = <&bus_leftbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	&bus_peril {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		devfreq = <&bus_leftbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	&bus_mfc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		devfreq = <&bus_leftbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	};