Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * AC timing parameters of LPDDR3 memories for a given speed-bin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The structures are based on LPDDR2 and extended where needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible : Should be "jedec,lpddr3-timings"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) The following properties represent AC timing parameters from the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) data-sheet of the device for a given speed-bin. All these properties are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) of type <u32> and the default unit is ps (pico seconds).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - tRFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - tRRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - tRPab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - tRPpb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - tRCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - tRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - tRAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - tWTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - tWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - tRTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - tW2W-C2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - tR2R-C2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - tFAW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - tXSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - tXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - tCKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - tCKESR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - tMRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	compatible	= "jedec,lpddr3-timings";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	reg		= <800000000>; /* workaround: it shows max-freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	min-freq	= <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	tRFC		= <65000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	tRRD		= <6000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	tRPab		= <12000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	tRPpb		= <12000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	tRCD		= <10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	tRC		= <33750>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	tRAS		= <23000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	tWTR		= <3750>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	tWR		= <7500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	tRTP		= <3750>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	tW2W-C2C	= <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	tR2R-C2C	= <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	tFAW		= <25000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	tXSR		= <70000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	tXP		= <3750>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	tCKE		= <3750>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	tCKESR		= <3750>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	tMRD		= <7000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };