^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "jedec,lpddr2-s4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - density : <u32> representing density in Mb (Mega bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - io-width : <u32> representing bus width. Possible values are 8, 16, and 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The following optional properties represent the minimum value of some AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) timing parameters of the DDR device in terms of number of clock cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) These values shall be obtained from the device data-sheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - tRRD-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - tWTR-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - tXP-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - tRTP-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - tCKE-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - tRPab-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - tRCD-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - tWR-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - tRASmin-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - tCKESR-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - tFAW-min-tck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Child nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "lpddr2-timings" provides AC timing parameters of the device for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) a given speed-bin. The user may provide the timings for as many
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) speed-bins as is required. Please see Documentation/devicetree/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) elpida_ECB240ABACN : lpddr2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) density = <2048>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) io-width = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) tRPab-min-tck = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) tRCD-min-tck = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) tWR-min-tck = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) tRASmin-min-tck = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) tRRD-min-tck = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) tWTR-min-tck = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tXP-min-tck = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) tRTP-min-tck = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) tCKE-min-tck = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) tCKESR-min-tck = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) tFAW-min-tck = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) compatible = "jedec,lpddr2-timings";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) min-freq = <10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) max-freq = <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tRPab = <21000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tRCD = <18000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tWR = <15000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tRAS-min = <42000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) tRRD = <10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tWTR = <7500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tXP = <7500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tRTP = <7500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) tCKESR = <15000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tDQSCK-max = <5500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tFAW = <50000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tZQCS = <90000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tZQCL = <360000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tZQinit = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) tRAS-max-ns = <70000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "jedec,lpddr2-timings";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) min-freq = <10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) max-freq = <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tRPab = <21000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tRCD = <18000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tWR = <15000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tRAS-min = <42000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tRRD = <10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tWTR = <10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tXP = <7500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tRTP = <7500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tCKESR = <15000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tDQSCK-max = <5500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tFAW = <50000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tZQCS = <90000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tZQCL = <360000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tZQinit = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tRAS-max-ns = <70000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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