Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Picochip picoXcell devices contain crypto offload engines that may be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) IPSEC and femtocell layer 2 ciphering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)     "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - reg : Offset and length of the register set for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - interrupts : The interrupt line from the SPAcc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - ref-clock : The input clock that drives the SPAcc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example SPAcc node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) spacc@10000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	compatible = "picochip,spacc-ipsec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	reg = <0x100000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	interrupt-parent = <&vic0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	interrupts = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	ref-clock = <&ipsec_clk>, "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };