Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) MediaTek cryptographic accelerators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "mediatek,eip97-crypto"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: Should contain the five crypto engines interrupts in numeric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	order. These are global system and four descriptor rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clocks: the clock used by the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names: Must contain "cryp".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - power-domains: Must contain a reference to the PM domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	crypto: crypto@1b240000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		compatible = "mediatek,eip97-crypto";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		reg = <0 0x1b240000 0 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		clock-names = "cryp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	};