^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) SEC 4 Device Tree Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright (C) 2008-2011 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) CONTENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) -Overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) -SEC 4 Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) -Job Ring Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) -Run Time Integrity Check (RTIC) Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) -Run Time Integrity Check (RTIC) Memory Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) -Secure Non-Volatile Storage (SNVS) Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) -Full Example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Accelerator and Assurance Module (CAAM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SEC 4 h/w can process requests from 2 types of sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 2. Job Rings (HW interface between cores & SEC 4 registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) High Speed Data Path Configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) such as the P4080. The number of simultaneous dequeues the QI can make is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) equal to the number of Descriptor Controller (DECO) engines in a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) dequeue from 5 subportals simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Job Ring Data Path Configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Each JR is located on a separate 4k page, they may (or may not) be made visible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SEC 4 Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Node defines the base address of the SEC 4 block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) This block specifies the address range of all global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) configuration registers for the SEC 4 block. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) also receives interrupts from the Run Time Integrity Check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (RTIC) function within the SEC 4 block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PROPERTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Definition: Must include "fsl,sec-v4.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - fsl,sec-era
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Definition: A standard property. Define the 'ERA' of the SEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - #address-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Definition: A standard property. Defines the number of cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for representing physical addresses in child nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - #size-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) Definition: A standard property. Defines the number of cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) for representing the size of physical addresses in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) child nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) Definition: A standard property. Specifies the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) address and length of the SEC4 configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Definition: A standard property. Specifies the physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) range of the SEC 4.0 register space (-SNVS not included). A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) triplet that includes the child address, parent address, &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) Value type: <prop_encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Definition: Specifies the interrupts generated by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) device. The value of the interrupts property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) consists of one interrupt specifier. The format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) of the specifier is defined by the binding document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) describing the node's interrupt parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) Usage: required if SEC 4.0 requires explicit enablement of clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Value type: <prop_encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) Definition: A list of phandle and clock specifier pairs describing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) the clocks required for enabling and disabling SEC 4.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Usage: required if SEC 4.0 requires explicit enablement of clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Definition: A list of clock name strings in the same order as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clocks property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Note: All other standard properties (see the Devicetree Specification)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) are allowed but are optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) iMX6QDL/SX requires four clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) crypto@300000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) compatible = "fsl,sec-v4.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) fsl,sec-era = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg = <0x300000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ranges = <0 0x300000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) interrupts = <92 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) <&clks IMX6QDL_CLK_CAAM_ACLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) <&clks IMX6QDL_CLK_CAAM_IPG>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) <&clks IMX6QDL_CLK_EIM_SLOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clock-names = "mem", "aclk", "ipg", "emi_slow";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) iMX6UL does only require three clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) crypto: crypto@2140000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) compatible = "fsl,sec-v4.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg = <0x2140000 0x3c000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ranges = <0 0x2140000 0x3c000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) <&clks IMX6UL_CLK_CAAM_ACLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) <&clks IMX6UL_CLK_CAAM_IPG>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clock-names = "mem", "aclk", "ipg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) Job Ring (JR) Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) Child of the crypto node defines data processing interface to SEC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) across the peripheral bus for purposes of processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cryptographic descriptors. The specified address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) range can be made visible to one (or more) cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) The interrupt defined for this node is controlled within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) the address range of this node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Definition: Must include "fsl,sec-v4.0-job-ring"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) Definition: Specifies a two JR parameters: an offset from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) the parent physical address and the length the JR registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) - fsl,liodn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) Usage: optional-but-recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) Definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) Specifies the LIODN to be used in conjunction with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) the ppid-to-liodn table that specifies the PPID to LIODN mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Needed if the PAMU is used. Value is a 12 bit value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) where value is a LIODN ID for this JR. This property is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) normally set by boot firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) Value type: <prop_encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) Definition: Specifies the interrupts generated by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) device. The value of the interrupts property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) consists of one interrupt specifier. The format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) of the specifier is defined by the binding document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) describing the node's interrupt parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) jr@1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) compatible = "fsl,sec-v4.0-job-ring";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reg = <0x1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) fsl,liodn = <0x081>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) interrupts = <88 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) Run Time Integrity Check (RTIC) Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) Child node of the crypto node. Defines a register space that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) contains up to 5 sets of addresses and their lengths (sizes) that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) will be checked at run time. After an initial hash result is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) calculated, these addresses are checked by HW to monitor any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) change. If any memory is modified, a Security Violation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) triggered (see SNVS definition).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) Definition: Must include "fsl,sec-v4.0-rtic".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) - #address-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) Definition: A standard property. Defines the number of cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for representing physical addresses in child nodes. Must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) have a value of 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) - #size-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) Definition: A standard property. Defines the number of cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for representing the size of physical addresses in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) child nodes. Must have a value of 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) Definition: A standard property. Specifies a two parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) an offset from the parent physical address and the length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) the SEC4 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) - ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) Definition: A standard property. Specifies the physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) range of the SEC 4 register space (-SNVS not included). A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) triplet that includes the child address, parent address, &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rtic@6000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) compatible = "fsl,sec-v4.0-rtic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reg = <0x6000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ranges = <0x0 0x6100 0xe00>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) Run Time Integrity Check (RTIC) Memory Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) A child node that defines individual RTIC memory regions that are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) perform run-time integrity check of memory areas that should not modified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) The node defines a register that contains the memory address &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) length (combined) and a second register that contains the hash result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) in big endian format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) Definition: Must include "fsl,sec-v4.0-rtic-memory".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) Definition: A standard property. Specifies two parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) an offset from the parent physical address and the length:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 1. The location of the RTIC memory address & length registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 2. The location RTIC hash result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) - fsl,rtic-region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) Usage: optional-but-recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) Definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) Specifies the HW address (36 bit address) for this region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) followed by the length of the HW partition to be checked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) the address is represented as a 64 bit quantity followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) by a 32 bit length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) - fsl,liodn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) Usage: optional-but-recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) Definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) Specifies the LIODN to be used in conjunction with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) the ppid-to-liodn table that specifies the PPID to LIODN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mapping. Needed if the PAMU is used. Value is a 12 bit value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) where value is a LIODN ID for this RTIC memory region. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) property is normally set by boot firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) rtic-a@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) compatible = "fsl,sec-v4.0-rtic-memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg = <0x00 0x20 0x100 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) fsl,liodn = <0x03c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) Secure Non-Volatile Storage (SNVS) Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) Node defines address range and the associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) interrupt for the SNVS function. This function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) monitors security state information & reports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) security violations. This also included rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) system power off and ON/OFF key.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) Definition: A standard property. Specifies the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) address and length of the SEC4 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) - #address-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) Definition: A standard property. Defines the number of cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for representing physical addresses in child nodes. Must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) have a value of 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) - #size-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) Definition: A standard property. Defines the number of cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) for representing the size of physical addresses in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) child nodes. Must have a value of 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) - ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) Definition: A standard property. Specifies the physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) range of the SNVS register space. A triplet that includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) the child address, parent address, & length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) Value type: <prop_encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) Definition: Specifies the interrupts generated by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) device. The value of the interrupts property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) consists of one interrupt specifier. The format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) of the specifier is defined by the binding document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) describing the node's interrupt parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) sec_mon@314000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) compatible = "fsl,sec-v4.0-mon", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reg = <0x314000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ranges = <0 0x314000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) interrupts = <93 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) A SNVS child node that defines SNVS LP RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) Value type: <prop_encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) Definition: Specifies the interrupts generated by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) device. The value of the interrupts property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) consists of one interrupt specifier. The format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) of the specifier is defined by the binding document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) describing the node's interrupt parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) - regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) Value type: <phandle>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) Definition: this is phandle to the register map node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) - offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) Usage: option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) Definition: LP register offset. default it is 0x34.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) Usage: optional, required if SNVS LP RTC requires explicit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enablement of clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) Value type: <prop_encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) Definition: a clock specifier describing the clock required for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) enabling and disabling SNVS LP RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) Usage: optional, required if SNVS LP RTC requires explicit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) enablement of clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) Definition: clock name string should be "snvs-rtc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sec_mon_rtc_lp@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) compatible = "fsl,sec-v4.0-mon-rtc-lp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) interrupts = <93 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regmap = <&snvs>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) offset = <0x34>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clocks = <&clks IMX7D_SNVS_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clock-names = "snvs-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) System ON/OFF key driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) The snvs-pwrkey is designed to enable POWER key function which controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) by SNVS ONOFF, the driver can report the status of POWER key and wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) system if pressed after system suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) Definition: Mush include "fsl,sec-v4.0-pwrkey".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) - interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) Value type: <prop_encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) Definition: The SNVS ON/OFF interrupt number to the CPU(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) - linux,keycode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) Usage: option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) Value type: <int>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) Definition: Keycode to emit, KEY_POWER by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) - wakeup-source:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) Usage: option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) Value type: <boo>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) Definition: Button can wake-up the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) - regmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) Usage: required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) Value type: <phandle>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) Definition: this is phandle to the register map node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) EXAMPLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) snvs-pwrkey@020cc000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) compatible = "fsl,sec-v4.0-pwrkey";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) regmap = <&snvs>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) interrupts = <0 4 0x4>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) linux,keycode = <116>; /* KEY_POWER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) wakeup-source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) FULL EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) crypto: crypto@300000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) compatible = "fsl,sec-v4.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) reg = <0x300000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ranges = <0 0x300000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) interrupts = <92 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sec_jr0: jr@1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) compatible = "fsl,sec-v4.0-job-ring";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) reg = <0x1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) interrupts = <88 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sec_jr1: jr@2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) compatible = "fsl,sec-v4.0-job-ring";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) reg = <0x2000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) interrupts = <89 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sec_jr2: jr@3000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) compatible = "fsl,sec-v4.0-job-ring";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) reg = <0x3000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) interrupts = <90 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) sec_jr3: jr@4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) compatible = "fsl,sec-v4.0-job-ring";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) reg = <0x4000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) interrupts = <91 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) rtic@6000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) compatible = "fsl,sec-v4.0-rtic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) reg = <0x6000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ranges = <0x0 0x6100 0xe00>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) rtic_a: rtic-a@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) compatible = "fsl,sec-v4.0-rtic-memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) reg = <0x00 0x20 0x100 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rtic_b: rtic-b@20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) compatible = "fsl,sec-v4.0-rtic-memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) reg = <0x20 0x20 0x200 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rtic_c: rtic-c@40 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) compatible = "fsl,sec-v4.0-rtic-memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) reg = <0x40 0x20 0x300 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) rtic_d: rtic-d@60 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) compatible = "fsl,sec-v4.0-rtic-memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg = <0x60 0x20 0x500 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) sec_mon: sec_mon@314000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) compatible = "fsl,sec-v4.0-mon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) reg = <0x314000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ranges = <0 0x314000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sec_mon_rtc_lp@34 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) compatible = "fsl,sec-v4.0-mon-rtc-lp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) regmap = <&sec_mon>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) offset = <0x34>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) interrupts = <93 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clocks = <&clks IMX7D_SNVS_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) clock-names = "snvs-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) snvs-pwrkey@020cc000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) compatible = "fsl,sec-v4.0-pwrkey";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) regmap = <&sec_mon>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) interrupts = <0 4 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) linux,keycode = <116>; /* KEY_POWER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) wakeup-source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) =====================================================================
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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