Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible : Should contain entries for this and backward compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)                              e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)     warning: SEC1 and SEC2 are mutually exclusive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg : Offset and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts : the SEC's interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - fsl,num-channels : An integer representing the number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - fsl,channel-fifo-len : An integer representing the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   descriptor pointers each channel fetch fifo can hold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - fsl,exec-units-mask : The bitmask representing what execution units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   (EUs) are available. It's a single 32-bit cell. EU information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   should be encoded following the SEC's Descriptor Header Dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   EU_SEL0 field documentation, i.e. as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	bit 0  = reserved - should be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	bit 1  = set if SEC has the ARC4 EU (AFEU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	bit 2  = set if SEC has the DES/3DES EU (DEU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	bit 3  = set if SEC has the message digest EU (MDEU/MDEU-A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	bit 4  = set if SEC has the random number generator EU (RNG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	bit 5  = set if SEC has the public key EU (PKEU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	bit 6  = set if SEC has the AES EU (AESU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	bit 7  = set if SEC has the Kasumi EU (KEU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	bit 8  = set if SEC has the CRC EU (CRCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) remaining bits are reserved for future SEC EUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - fsl,descriptor-types-mask : The bitmask representing what descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   are available. It's a single 32-bit cell. Descriptor type information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   field documentation, i.e. as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	bit 0  = set if SEC supports the aesu_ctr_nonsnoop desc. type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	bit 1  = set if SEC supports the ipsec_esp descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	bit 2  = set if SEC supports the common_nonsnoop desc. type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	bit 3  = set if SEC supports the 802.11i AES ccmp desc. type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	bit 4  = set if SEC supports the hmac_snoop_no_afeu desc. type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	bit 5  = set if SEC supports the srtp descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	bit 6  = set if SEC supports the non_hmac_snoop_no_afeu desc.type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	bit 7  = set if SEC supports the pkeu_assemble descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	bit 8  = set if SEC supports the aesu_key_expand_output desc.type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	bit 9  = set if SEC supports the pkeu_ptmul descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   ..and so on and so forth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* MPC8548E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	crypto@30000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		compatible = "fsl,sec2.1", "fsl,sec2.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		reg = <0x30000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		interrupts = <29 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		fsl,num-channels = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		fsl,channel-fifo-len = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		fsl,exec-units-mask = <0xfe>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		fsl,descriptor-types-mask = <0x12b0ebf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	};