^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) TI CPUFreq and OPP bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) families support different OPPs depending on the silicon variant in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) The ti-cpufreq driver can use revision and an efuse value from the SoC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) provide the OPP framework with supported hardware information. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) used to determine which OPPs from the operating-points-v2 table get enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) when it is parsed by the OPP framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) In 'cpus' nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - operating-points-v2: Phandle to the operating-points-v2 table to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) In 'operating-points-v2' table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - compatible: Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) omap34xx, omap36xx and am3517 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - syscon: A phandle pointing to a syscon node representing the control module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) register space of the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - "vdd-supply", "vbb-supply": to define two regulators for dra7xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - "cpu0-supply", "vbb-supply": to define two regulators for omap36xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) For each opp entry in 'operating-points-v2' table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - opp-supported-hw: Two bitfields indicating:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 1. Which revision of the SoC the OPP is supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 2. Which eFuse bits indicate this OPP is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) A bitwise AND is performed against these values and if any bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) matches, the OPP gets enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* From arch/arm/boot/dts/am33xx.dtsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) compatible = "arm,cortex-a8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) operating-points-v2 = <&cpu0_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) clocks = <&dpll_mpu_ck>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clock-names = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) clock-latency = <300000>; /* From omap-cpufreq driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * cpu0 has different OPPs depending on SoC revision and some on revisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cpu0_opp_table: opp-table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) compatible = "operating-points-v2-ti-cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) syscon = <&scm_conf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * The three following nodes are marked with opp-suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * because they can not be enabled simultaneously on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * single SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) opp50-300000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) opp-hz = /bits/ 64 <300000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) opp-microvolt = <950000 931000 969000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) opp-supported-hw = <0x06 0x0010>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) opp100-275000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) opp-hz = /bits/ 64 <275000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) opp-microvolt = <1100000 1078000 1122000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) opp-supported-hw = <0x01 0x00FF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) opp100-300000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) opp-hz = /bits/ 64 <300000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) opp-microvolt = <1100000 1078000 1122000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) opp-supported-hw = <0x06 0x0020>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) opp100-500000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) opp-hz = /bits/ 64 <500000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) opp-microvolt = <1100000 1078000 1122000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) opp-supported-hw = <0x01 0xFFFF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) opp100-600000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) opp-hz = /bits/ 64 <600000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) opp-microvolt = <1100000 1078000 1122000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) opp-supported-hw = <0x06 0x0040>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) opp120-600000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) opp-hz = /bits/ 64 <600000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) opp-microvolt = <1200000 1176000 1224000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) opp-supported-hw = <0x01 0xFFFF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) opp120-720000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) opp-hz = /bits/ 64 <720000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) opp-microvolt = <1200000 1176000 1224000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) opp-supported-hw = <0x06 0x0080>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) oppturbo-720000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) opp-hz = /bits/ 64 <720000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) opp-microvolt = <1260000 1234800 1285200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) opp-supported-hw = <0x01 0xFFFF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) oppturbo-800000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) opp-hz = /bits/ 64 <800000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) opp-microvolt = <1260000 1234800 1285200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) opp-supported-hw = <0x06 0x0100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) oppnitro-1000000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) opp-hz = /bits/ 64 <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) opp-microvolt = <1325000 1298500 1351500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) opp-supported-hw = <0x04 0x0200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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