^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Qualcomm Technologies, Inc. CPUFREQ Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) SoCs to manage frequency in hardware. It is capable of controlling frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) for multiple clusters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Value type: <phandle> From common clock binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Definition: clock handle for XO clock and GPLL0 clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Value type: <string> From common clock binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Definition: must be "xo", "alternate".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Definition: Addresses and sizes for the memory of the HW bases in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) each frequency domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - reg-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Usage: Optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Definition: Frequency domain name i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "freq-domain0", "freq-domain1".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - #freq-domain-cells:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Usage: required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Definition: Number of cells in a freqency domain specifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Property qcom,freq-domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Devices supporting freq-domain must set their "qcom,freq-domain" property with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DCVS state together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CPU0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) reg = <0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) next-level-cache = <&L2_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) qcom,freq-domain = <&cpufreq_hw 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) L2_0: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) L3_0: l3-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CPU1: cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = <0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) next-level-cache = <&L2_100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) qcom,freq-domain = <&cpufreq_hw 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) L2_100: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CPU2: cpu@200 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = <0x0 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) next-level-cache = <&L2_200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) qcom,freq-domain = <&cpufreq_hw 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) L2_200: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CPU3: cpu@300 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = <0x0 0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) next-level-cache = <&L2_300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) qcom,freq-domain = <&cpufreq_hw 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) L2_300: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CPU4: cpu@400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = <0x0 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) next-level-cache = <&L2_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) qcom,freq-domain = <&cpufreq_hw 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) L2_400: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CPU5: cpu@500 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg = <0x0 0x500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) next-level-cache = <&L2_500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) qcom,freq-domain = <&cpufreq_hw 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) L2_500: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CPU6: cpu@600 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg = <0x0 0x600>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) next-level-cache = <&L2_600>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) qcom,freq-domain = <&cpufreq_hw 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) L2_600: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CPU7: cpu@700 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) compatible = "qcom,kryo385";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg = <0x0 0x700>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) next-level-cache = <&L2_700>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) qcom,freq-domain = <&cpufreq_hw 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) L2_700: l2-cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) next-level-cache = <&L3_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cpufreq_hw: cpufreq@17d43000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) compatible = "qcom,cpufreq-hw";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) reg-names = "freq-domain0", "freq-domain1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clock-names = "xo", "alternate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #freq-domain-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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