^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Binding for MediaTek's CPUFreq driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - clock-names: Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "cpu" - The multiplexer for clock input of CPU cluster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) source (usually MAINPLL) when the original CPU PLL is under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) transition and not stable yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) generic clock consumer properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) for detail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - proc-supply: Regulator for Vproc of CPU cluster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) needs to do "voltage tracking" to step by step scale up/down Vproc and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Vsram to fit SoC specific needs. When absent, the voltage scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) flow is handled by hardware, hence no software "voltage tracking" is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - #cooling-cells:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) For details, please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Example 1 (MT7623 SoC):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) cpu_opp_table: opp_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) opp-598000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) opp-hz = /bits/ 64 <598000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) opp-microvolt = <1050000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) opp-747500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) opp-hz = /bits/ 64 <747500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) opp-microvolt = <1050000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) opp-1040000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) opp-hz = /bits/ 64 <1040000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) opp-microvolt = <1150000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) opp-1196000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) opp-hz = /bits/ 64 <1196000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) opp-microvolt = <1200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) opp-1300000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) opp-hz = /bits/ 64 <1300000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) opp-microvolt = <1300000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) cpu0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clocks = <&infracfg CLK_INFRA_CPUSEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) <&apmixedsys CLK_APMIXED_MAINPLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clock-names = "cpu", "intermediate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #cooling-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cpu@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg = <0x3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) operating-points-v2 = <&cpu_opp_table>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Example 2 (MT8173 SoC):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cpu_opp_table_a: opp_table_a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) opp-507000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) opp-hz = /bits/ 64 <507000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) opp-microvolt = <859000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) opp-702000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) opp-hz = /bits/ 64 <702000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) opp-microvolt = <908000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) opp-1001000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) opp-hz = /bits/ 64 <1001000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) opp-microvolt = <983000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) opp-1105000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) opp-hz = /bits/ 64 <1105000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) opp-microvolt = <1009000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) opp-1183000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) opp-hz = /bits/ 64 <1183000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) opp-microvolt = <1028000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) opp-1404000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) opp-hz = /bits/ 64 <1404000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) opp-microvolt = <1083000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) opp-1508000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) opp-hz = /bits/ 64 <1508000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) opp-microvolt = <1109000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) opp-1573000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) opp-hz = /bits/ 64 <1573000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) opp-microvolt = <1125000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) cpu_opp_table_b: opp_table_b {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) compatible = "operating-points-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) opp-shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) opp-507000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) opp-hz = /bits/ 64 <507000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) opp-microvolt = <828000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) opp-702000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) opp-hz = /bits/ 64 <702000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) opp-microvolt = <867000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) opp-1001000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) opp-hz = /bits/ 64 <1001000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) opp-microvolt = <927000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) opp-1209000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) opp-hz = /bits/ 64 <1209000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) opp-microvolt = <968000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) opp-1404000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) opp-hz = /bits/ 64 <1007000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) opp-microvolt = <1028000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) opp-1612000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) opp-hz = /bits/ 64 <1612000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) opp-microvolt = <1049000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) opp-1807000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) opp-hz = /bits/ 64 <1807000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) opp-microvolt = <1089000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) opp-1989000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) opp-hz = /bits/ 64 <1989000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) opp-microvolt = <1125000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cpu0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg = <0x000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cpu-idle-states = <&CPU_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clocks = <&infracfg CLK_INFRA_CA53SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) <&apmixedsys CLK_APMIXED_MAINPLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clock-names = "cpu", "intermediate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) operating-points-v2 = <&cpu_opp_table_a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cpu1: cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg = <0x001>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cpu-idle-states = <&CPU_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clocks = <&infracfg CLK_INFRA_CA53SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) <&apmixedsys CLK_APMIXED_MAINPLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clock-names = "cpu", "intermediate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) operating-points-v2 = <&cpu_opp_table_a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cpu2: cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg = <0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cpu-idle-states = <&CPU_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clocks = <&infracfg CLK_INFRA_CA57SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) <&apmixedsys CLK_APMIXED_MAINPLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clock-names = "cpu", "intermediate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) operating-points-v2 = <&cpu_opp_table_b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cpu3: cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = <0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cpu-idle-states = <&CPU_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clocks = <&infracfg CLK_INFRA_CA57SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) <&apmixedsys CLK_APMIXED_MAINPLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clock-names = "cpu", "intermediate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) operating-points-v2 = <&cpu_opp_table_b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) &cpu0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) proc-supply = <&mt6397_vpca15_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) &cpu1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) proc-supply = <&mt6397_vpca15_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) &cpu2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) proc-supply = <&da9211_vcpu_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sram-supply = <&mt6397_vsramca7_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &cpu3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) proc-supply = <&da9211_vcpu_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) sram-supply = <&mt6397_vsramca7_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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