^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device Tree Clock bindings for the Zynq 7000 EPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Zynq EPP has several different clk providers, each with there own bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The purpose of this document is to document their usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) See clock_bindings.txt for more information on the generic clock bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) See Chapter 25 of Zynq TRM for more information about Zynq clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) == Clock Controller ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The clock controller is a logical abstraction of Zynq's clock tree. It reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) required input clock frequencies from the devicetree and acts as clock provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) for all clock consumers of PS clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - #clock-cells : Must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - compatible : "xlnx,ps7-clkc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) (usually 33 MHz oscillators are used for Zynq platforms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - clock-output-names : List of strings used to name the clock outputs. Shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) a list of the outputs given below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - clocks : as described in the clock bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clock-names : as described in the clock bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - fclk-enable : Bit mask to enable FCLKs statically at boot time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FCLK will only be enabled if it is actually running at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) boot time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Clock inputs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) The following strings are optional parameters to the 'clock-names' property in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) order to provide an optional (E)MIO clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - swdt_ext_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - gem0_emio_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - gem1_emio_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - mio_clk_XX # with XX = 00..53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Clock outputs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0: armpll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 1: ddrpll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 2: iopll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 3: cpu_6or4x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 4: cpu_3or2x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 5: cpu_2x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 6: cpu_1x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 7: ddr2x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 8: ddr3x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 9: dci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 10: lqspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 11: smc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 12: pcap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 13: gem0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 14: gem1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 15: fclk0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 16: fclk1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 17: fclk2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 18: fclk3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 19: can0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 20: can1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 21: sdio0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 22: sdio1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 23: uart0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 24: uart1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 25: spi0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 26: spi1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 27: dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 28: usb0_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 29: usb1_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 30: gem0_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 31: gem1_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 32: sdio0_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 33: sdio1_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 34: spi0_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 35: spi1_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 36: can0_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 37: can1_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 38: i2c0_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 39: i2c1_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 40: uart0_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 41: uart1_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 42: gpio_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 43: lqspi_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 44: smc_aper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 45: swdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 46: dbg_trc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 47: dbg_apb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clkc: clkc@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) compatible = "xlnx,ps7-clkc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ps-clk-frequency = <33333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = <0x100 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "dma", "usb0_aper", "usb1_aper", "gem0_aper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "gem1_aper", "sdio0_aper", "sdio1_aper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "dbg_trc", "dbg_apb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) # optional props
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clocks = <&clkc 16>, <&clk_foo>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clock-names = "gem1_emio_clk", "can_mio_clk_23";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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