Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device Tree Clock bindings for ZTE zx296718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding uses the common clock binding[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible : shall be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"zte,zx296718-topcrm":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		zx296718 top clock selection, divider and gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"zte,zx296718-lsp0crm" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"zte,zx296718-lsp1crm":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		zx296718 device level clock selection and gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	"zte,zx296718-audiocrm":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		zx296718 audio clock selection, divider and gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg: Address and length of the register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) for the full list of zx296718 clock IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) topclk: topcrm@1461000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)         compatible = "zte,zx296718-topcrm-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)         reg = <0x01461000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)         #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) usbphy0:usb-phy0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	compatible = "zte,zx296718-usb-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	clocks = <&topclk USB20_PHY_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	clock-names = "phyclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };