Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device Tree Clock bindings for ZTE zx296702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding uses the common clock binding[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible : shall be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"zte,zx296702-topcrm-clk":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		zx296702 top clock selection, divider and gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"zte,zx296702-lsp0crpm-clk" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"zte,zx296702-lsp1crpm-clk":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		zx296702 device level clock selection and gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg: Address and length of the register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) for the full list of zx296702 clock IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) topclk: topcrm@09800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)         compatible = "zte,zx296702-topcrm-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)         reg = <0x09800000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)         #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) uart0: serial@09405000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)         compatible = "zte,zx296702-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)         reg = <0x09405000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)         clocks = <&lsp1clk ZX296702_UART0_PCLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };