^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device Tree Clock bindings for APM X-Gene
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This binding uses the common clock binding[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible : shall be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "apm,xgene-pmd-clock" - for a X-Gene PMD clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "apm,xgene-device-clock" - for a X-Gene device clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Required properties for SoC or PCP PLL clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg : shall be the physical PLL register address for the pll clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clocks : shall be the input parent clock phandle for the clock. This should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) be the reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - #clock-cells : shall be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clock-output-names : shall be the name of the PLL referenced by derive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties for PLL clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - clock-names : shall be the name of the PLL. If missing, use the device name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Required properties for PMD clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - reg : shall be the physical register address for the pmd clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - clocks : shall be the input parent clock phandle for the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #clock-cells : shall be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - clock-output-names : shall be the name of the clock referenced by derive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Optional properties for PLL clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - clock-names : shall be the name of the clock. If missing, use the device name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Required properties for device clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - reg : shall be a list of address and length pairs describing the CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reset and/or the divider. Either may be omitted, but at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) one must be present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - reg-names : shall be a string list describing the reg resource. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) may include "csr-reg" and/or "div-reg". If this property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) is not present, the reg property is assumed to describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) only "csr-reg".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - clocks : shall be the input parent clock phandle for the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - #clock-cells : shall be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - clock-output-names : shall be the name of the device referenced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Optional properties for device clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - clock-names : shall be the name of the device clock. If missing, use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) device name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - csr-offset : Offset to the CSR reset register from the reset address base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Default is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - csr-mask : CSR reset mask bit. Default is 0xF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - enable-offset : Offset to the enable register from the reset address base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Default is 0x8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - enable-mask : CSR enable mask bit. Default is 0xF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - divider-offset : Offset to the divider CSR register from the divider base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Default is 0x0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - divider-width : Width of the divider register. Default is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - divider-shift : Bit shift of the divider register. Default is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pcppll: pcppll@17000100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) compatible = "apm,xgene-pcppll-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clocks = <&refclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clock-names = "pcppll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg = <0x0 0x17000100 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clock-output-names = "pcppll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) type = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pmd0clk: pmd0clk@7e200200 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) compatible = "apm,xgene-pmd-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clocks = <&pmdpll 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg = <0x0 0x7e200200 0x0 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clock-output-names = "pmd0clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) socpll: socpll@17000120 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) compatible = "apm,xgene-socpll-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clocks = <&refclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clock-names = "socpll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = <0x0 0x17000120 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clock-output-names = "socpll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) type = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) qmlclk: qmlclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) compatible = "apm,xgene-device-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clocks = <&socplldiv2 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clock-names = "qmlclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = <0x0 0x1703C000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg-name = "csr-reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clock-output-names = "qmlclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ethclk: ethclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) compatible = "apm,xgene-device-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clocks = <&socplldiv2 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clock-names = "ethclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg = <0x0 0x17000000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg-names = "div-reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) divider-offset = <0x238>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) divider-width = <0x9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) divider-shift = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clock-output-names = "ethclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) apbclk: apbclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) compatible = "apm,xgene-device-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clocks = <&ahbclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clock-names = "apbclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg = <0x0 0x1F2AC000 0x0 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x0 0x1F2AC000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg-names = "csr-reg", "div-reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) csr-offset = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) csr-mask = <0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enable-offset = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enable-mask = <0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) divider-offset = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) divider-width = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) divider-shift = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) flags = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clock-output-names = "apbclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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