Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device Tree Clock bindings for arch-vt8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding uses the common clock binding[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible : shall be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	"wm,wm8650-pll-clock" - for a WM8650 PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	"wm,wm8750-pll-clock" - for a WM8750 PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"wm,wm8850-pll-clock" - for a WM8850 PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"via,vt8500-device-clock" - for a VT/WM device clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Required properties for PLL clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg : shall be the control register offset from PMC base for the pll clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks : shall be the input parent clock phandle for the clock. This should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	be the reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #clock-cells : from common clock binding; shall be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Required properties for device clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - clocks : shall be the input parent clock phandle for the clock. This should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	be a pll output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - #clock-cells : from common clock binding; shall be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Device Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Device clocks are required to have one or both of the following sets of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Gated device clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - enable-reg : shall be the register offset from PMC base for the enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - enable-bit : shall be the bit within enable-reg to enable/disable the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Divisor device clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Required property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - divisor-reg : shall be the register offset from PMC base for the divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Optional property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	if not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ref25: ref25M {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	clock-frequency = <25000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) plla: plla {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	compatible = "wm,wm8650-pll-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	clocks = <&ref25>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	reg = <0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) sdhc: sdhc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	compatible = "via,vt8500-device-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	clocks = <&pllb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	divisor-reg = <0x328>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	divisor-mask = <0x3f>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	enable-reg = <0x254>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	enable-bit = <18>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };