Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Clock bindings for Freescale Vybrid VF610 SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "fsl,vf610-ccm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Address and length of the register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - #clock-cells: Should be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clocks: list of clock identifiers which are external input clocks to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	given clock controller. Please refer the next section to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	the input clocks for a given controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clock-names: list of names of clocks which are exteral input clocks to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	given clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Input clocks for top clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	- sxosc (external crystal oscillator 32KHz, recommended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	- fxosc (external crystal oscillator 24MHz, recommended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	- audio_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	- enet_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) for the full list of VF610 clock IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) clks: ccm@4006b000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	compatible = "fsl,vf610-ccm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	reg = <0x4006b000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	clocks = <&sxosc>, <&fxosc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	clock-names = "sxosc", "fxosc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) uart1: serial@40028000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	compatible = "fsl,vf610-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	reg = <0x40028000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	interrupts = <0 62 0x04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	clocks = <&clks VF610_CLK_UART1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	clock-names = "ipg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };