Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Clock bindings for ST-Ericsson Ux500 clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : shall contain only one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   "stericsson,u8500-clks"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   "stericsson,u8540-clks"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   "stericsson,u9540-clks"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg : shall contain base register location and length for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   CLKRST4, which does not exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required subnodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - prcmu-clock: a subnode with one clock cell for PRCMU (power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   reset, control unit) clocks. The cell indicates which PRCMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   clock in the prcmu-clock node the consumer wants to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - prcc-periph-clock: a subnode with two clock cells for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   PRCC (programmable reset- and clock controller) peripheral clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   The first cell indicates which PRCC block the consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   wants to use, possible values are 1, 2, 3, 5, 6. The second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   cell indicates which clock inside the PRCC block it wants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   possible values are 0 thru 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - prcc-kernel-clock: a subnode with two clock cells for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   PRCC (programmable reset- and clock controller) kernel clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   The first cell indicates which PRCC block the consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   wants to use, possible values are 1, 2, 3, 5, 6. The second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   cell indicates which clock inside the PRCC block it wants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   possible values are 0 thru 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - rtc32k-clock: a subnode with zero clock cells for the 32kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   RTC clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   with zero clock cells.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	compatible = "stericsson,u8500-clks";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	 * Registers for the CLKRST block on peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	 * groups 1, 2, 3, 5, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	    <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	    <0xa03cf000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	prcmu_clk: prcmu-clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	prcc_pclk: prcc-periph-clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		#clock-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	prcc_kclk: prcc-kernel-clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		#clock-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	rtc_clk: rtc32k-clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	smp_twd_clk: smp-twd-clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };