Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Texas Instruments clkctrl clock binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Texas Instruments SoCs can have a clkctrl clock controller for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) interconnect target module. The clkctrl clock controller manages functional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) and interface clocks for each module. Each clkctrl controller can also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) gate one or more optional functional clocks for a module, and can have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) or more clock muxes. There is a clkctrl clock controller typically for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) interconnect target module on omap4 and later variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The clock consumers can specify the index of the clkctrl clock using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the hardware offset from the clkctrl instance register space. The optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) clocks can be specified by clkctrl hardware offset and the index of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) optional clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) For more information, please see the Linux clock framework binding at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Documentation/devicetree/bindings/clock/clock-bindings.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - compatible : shall be "ti,clkctrl" or a clock domain specific name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	       "ti,clkctrl-l4-cfg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	       "ti,clkctrl-l4-per"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	       "ti,clkctrl-l4-secure"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	       "ti,clkctrl-l4-wkup"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - #clock-cells : shall contain 2 with the first entry being the instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		 offset from the clock domain base and the second being the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		 clock index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - reg : clock registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Example: Clock controller node on omap 4430:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) &cm2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	l4per: cm@1400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		cm_l4per@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			cm_l4per_clkctrl: clock@20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 				compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 				reg = <0x20 0x1b0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 				#clock-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP4_CLKCTRL_OFFSET		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MODULEMODE_HWCTRL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MODULEMODE_SWCTRL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP4_GPTIMER10_CLKTRL		OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP4_GPTIMER11_CLKTRL		OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP4_GPTIMER2_CLKTRL		OMAP4_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP4_GPIO2_CLKCTRL		OMAP_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Example: Clock consumer node for GPIO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) &gpio2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)        clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		 &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };