Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Sigma Designs Tango4 Clock Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) for RAM and various peripheral devices). The clock binding described here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) is applicable to all Tango4 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - compatible: should be "sigma,tango4-clkgen".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg: physical base address of the device and length of memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks: phandle of the input clock (crystal oscillator).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clock-output-names: should be "cpuclk" and "sysclk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #clock-cells: should be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	clkgen: clkgen@10000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		compatible = "sigma,tango4-clkgen";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		reg = <0x10000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		clocks = <&xtal>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		clock-output-names = "cpuclk", "sysclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	};