Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Clock bindings for ST-Ericsson U300 System Controller Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Bindings for the gated system controller clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible: must be "stericsson,u300-syscon-clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #clock-cells: must be <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clock-type: specifies the type of clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   0 = slow clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   1 = fast clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   2 = rest/remaining clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clock-id: specifies the clock in the type range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: parent clock(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) The available clocks per type are as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Type:  ID:   Clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 0      0     Slow peripheral bridge clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 0      1     UART0 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 0      4     GPIO clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 0      6     RTC clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 0      7     Application timer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0      8     Access timer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 1      0     Fast peripheral bridge clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 1      1     I2C bus 0 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 1      2     I2C bus 1 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 1      5     MMC interface peripheral (silicon) clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 1      6     SPI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 2      3     CPU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 2      4     DMA controller clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 2      5     External Memory Interface (EMIF) clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 2      6     NAND flask interface clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 2      8     XGAM graphics engine clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 2      9     Shared External Memory Interface (SEMI) clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 2      10    AHB Subsystem Bridge clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 2      12    Interrupt controller clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) gpio_clk: gpio_clk@13M {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	compatible = "stericsson,u300-syscon-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	clock-type = <0>; /* Slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	clock-id = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clocks = <&slow_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) gpio: gpio@c0016000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	compatible = "stericsson,gpio-coh901";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	(...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	clocks = <&gpio_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Bindings for the MMC/SD card clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - compatible: must be "stericsson,u300-syscon-mclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - #clock-cells: must be <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - clocks: parent clock(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mmc_mclk: mmc_mclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	compatible = "stericsson,u300-syscon-mclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	clocks = <&mmc_pclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mmcsd: mmcsd@c0001000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	compatible = "arm,pl18x", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	clocks = <&mmc_pclk>, <&mmc_mclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	clock-names = "apb_pclk", "mclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	(...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };