Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Clock bindings for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "sirf,prima2-clkc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Address and length of the register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: Should contain clock controller interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #clock-cells: Should be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ID in its "clocks" phandle cell.  The following is a full list of prima2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) clocks and IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	Clock			ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	rtc			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	osc             	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	pll1            	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	pll2            	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	pll3            	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	mem             	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	sys             	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	security        	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	dsp             	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	gps             	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	mf              	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	io              	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	cpu             	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	uart0           	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	uart1           	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	uart2           	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	tsc             	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	i2c0            	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	i2c1            	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	spi0            	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	spi1            	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	pwmc            	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	efuse           	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	pulse           	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	dmac0           	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	dmac1           	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	nand            	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	audio           	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	usp0            	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	usp1            	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	usp2            	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	vip             	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	gfx             	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	mm              	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	lcd             	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	vpp             	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	mmc01           	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	mmc23           	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	mmc45           	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	usbpll          	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	usb0            	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	usb1			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clks: clock-controller@88000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	compatible = "sirf,prima2-clkc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	reg = <0x88000000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	interrupts = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) i2c0: i2c@b00e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	cell-index = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	compatible = "sirf,prima2-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	reg = <0xb00e0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	interrupts = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	clocks = <&clks 17>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };