^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Imagination Technologies Pistachio SoC clock controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Pistachio has four clock controllers (core clock, peripheral clock, peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) general control, and top general control) which are instantiated individually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) from the device-tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) External clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) There are three external inputs to the clock controllers which should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) defined with the following clock-output-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - "xtal": External 52Mhz oscillator (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - "audio_clk_in": Alternate audio reference clock (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - "enet_clk_in": Alternate ethernet PHY clock (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Core clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) The core clock controller generates clocks for the CPU, RPU (WiFi + BT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) co-processor), audio, and several peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - compatible: Must be "img,pistachio-clk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg: Must contain the base address and length of the core clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - #clock-cells: Must be 1. The single cell is the clock identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - clocks: Must contain an entry for each clock in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - clock-names: Must include "xtal" (see "External clocks") and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) top-level general control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) clk_core: clock-controller@18144000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) compatible = "img,pistachio-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) reg = <0x18144000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) <&cr_top EXT_CLK_ENET_IN>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Peripheral clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) The peripheral clock controller generates clocks for the DDR, ROM, and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) peripherals. The peripheral system clock ("periph_sys") generated by the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clock controller is the input clock to the peripheral clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - compatible: Must be "img,pistachio-periph-clk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - reg: Must contain the base address and length of the peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - #clock-cells: Must be 1. The single cell is the clock identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - clocks: Must contain an entry for each clock in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - clock-names: Must include "periph_sys", the peripheral system clock generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) by the core clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk_periph: clock-controller@18144800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) compatible = "img,pistachio-clk-periph";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) reg = <0x18144800 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clocks = <&clk_core CLK_PERIPH_SYS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clock-names = "periph_sys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Peripheral general control:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) The peripheral general control block generates system interface clocks and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) resets for various peripherals. It also contains miscellaneous peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) control registers. The system clock ("sys") generated by the peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) controller is the input clock to the system clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - compatible: Must include "img,pistachio-periph-cr" and "syscon".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - reg: Must contain the base address and length of the peripheral general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - #clock-cells: Must be 1. The single cell is the clock identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - clocks: Must contain an entry for each clock in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - clock-names: Must include "sys", the system clock generated by the peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) cr_periph: syscon@18144800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) compatible = "img,pistachio-cr-periph", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg = <0x18148000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clock-names = "sys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) Top-level general control:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) The top-level general control block contains miscellaneous control registers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) gates for the external clocks "audio_clk_in" and "enet_clk_in".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - compatible: Must include "img,pistachio-cr-top" and "syscon".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - reg: Must contain the base address and length of the top-level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - clocks: Must contain an entry for each clock in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) - clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "External clocks").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) - #clock-cells: Must be 1. The single cell is the clock identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cr_top: syscon@18144800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) compatible = "img,pistachio-cr-top", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg = <0x18149000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clocks = <&audio_refclk>, <&ext_enet_in>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clock-names = "audio_clk_in", "enet_clk_in";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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