Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device Tree Clock bindings for cpu clock of Marvell EBU platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : shall be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - reg : Address and length of the clock complex register set, followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)         by address and length of the PMU DFS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - #clock-cells : should be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks : shall be the input parent clock phandle for the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) cpuclk: clock-complex@d0018700 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	compatible = "marvell,armada-xp-cpu-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	clocks = <&coreclk 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	compatible = "marvell,sheeva-v7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	clocks = <&cpuclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };