Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Milbeaut SoCs Clock Controller Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Taichi Sugaya <sugaya.taichi@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   Milbeaut SoCs Clock controller is an integrated clock controller, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   generates and supplies to all modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   This binding uses common clock bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)           - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)               - socionext,milbeaut-m10v-ccu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     description: external clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)     const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   # Clock controller node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)     m10v-clk-ctrl@1d021000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)         compatible = "socionext,milbeaut-m10v-clk-ccu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)         reg = <0x1d021000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)         #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)         clocks = <&clki40mhz>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   # Required an external clock for Clock controller node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)     clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)         clki40mhz: clki40mhz {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)             compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)             #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)             clock-frequency = <40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)         };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)         /* other clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)   # The clock consumer shall specify the desired clock-output of the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)   # controller as below by specifying output-id in its "clk" phandle cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)   # 2: uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)   # 4: 32-bit timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)   # 7: UHS-I/II
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)     serial@1e700010 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)         compatible = "socionext,milbeaut-usio-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)         reg = <0x1e700010 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)         interrupts = <0 141 0x4>, <0 149 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)         interrupt-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)         clocks = <&clk 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ...