Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * NXP LPC1850 CREG clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) control registers for two low speed clocks. One of the clocks is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 32 kHz oscillator driver with power up/down and clock gating. Next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) These clocks are used by the RTC and the Event Router peripherials.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) The 32 kHz can also be routed to other peripherials to enable low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) power modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) This binding uses the common clock binding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)     Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	Should be "nxp,lpc1850-creg-clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #clock-cells:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	Shall have value <1>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	Shall contain a phandle to the fixed 32 kHz crystal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) The creg-clk node must be a child of the creg syscon node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) The following clocks are available from the clock node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Clock ID	Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)    0		 1 kHz clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)    1		32 kHz Oscillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	creg: syscon@40043000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		reg = <0x40043000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		creg_clk: clock-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			compatible = "nxp,lpc1850-creg-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			clocks = <&xtal32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	rtc: rtc@40046000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		clock-names = "rtc", "reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };