^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * NXP LPC1850 Clock Generation Unit (CGU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The CGU generates multiple independent clocks for the core and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) peripheral blocks of the LPC18xx. Each independent clock is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) a base clock and itself is one of the inputs to the two Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Control Units (CCUs) which control the branch clocks to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) individual peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) The CGU selects the inputs to the clock generators from multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) clock sources, controls the clock generation, and routes the outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) of the clock generators through the clock source bus to the output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) stages. Each output stage provides an independent clock source and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) corresponds to one of the base clocks for the LPC18xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - Above text taken from NXP LPC1850 User Manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) This binding uses the common clock binding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Should be "nxp,lpc1850-cgu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Shall define the base and range of the address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) containing clock control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - #clock-cells:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Shall have value <1>. The permitted clock-specifier values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) are the base clock numbers defined below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Shall contain a list of phandles for the external input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) sources to the CGU. The list shall be in the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - clock-indices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Shall be an ordered list of numbers defining the base clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) number provided by the CGU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - clock-output-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Shall be an ordered list of strings defining the names of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) the clocks provided by the CGU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Which base clocks that are available on the CGU depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) specific LPC part. Base clocks are numbered from 0 to 27.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Number: Name: Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 1 BASE_USB0_CLK Base clock for USB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SPI, and SGPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 3 BASE_USB1_CLK Base clock for USB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 4 BASE_CPU_CLK System base clock for ARM Cortex-M core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) and APB peripheral blocks #0 and #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 5 BASE_SPIFI_CLK Base clock for SPIFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 6 BASE_SPI_CLK Base clock for SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 9 BASE_APB1_CLK Base clock for APB peripheral block # 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 10 BASE_APB3_CLK Base clock for APB peripheral block # 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 11 BASE_LCD_CLK Base clock for LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 12 BASE_ADCHS_CLK Base clock for ADCHS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 13 BASE_SDIO_CLK Base clock for SD/MMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 14 BASE_SSP0_CLK Base clock for SSP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 15 BASE_SSP1_CLK Base clock for SSP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 16 BASE_UART0_CLK Base clock for UART0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 17 BASE_UART1_CLK Base clock for UART1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 18 BASE_UART2_CLK Base clock for UART2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 19 BASE_UART3_CLK Base clock for UART3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 20 BASE_OUT_CLK Base clock for CLKOUT pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 24-21 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 25 BASE_AUDIO_CLK Base clock for audio system (I2S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BASE_ADCHS_CLK is only available on LPC4370.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Example board file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) xtal: xtal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clock-frequency = <12000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) xtal32: xtal32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clock-frequency = <32768>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enet_rx_clk: enet_rx_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clock-frequency = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clock-output-names = "enet_rx_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enet_tx_clk: enet_tx_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clock-frequency = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clock-output-names = "enet_tx_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) gp_clkin: gp_clkin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clock-frequency = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clock-output-names = "gp_clkin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cgu: clock-controller@40050000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) compatible = "nxp,lpc1850-cgu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg = <0x40050000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* A CGU and CCU clock consumer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) lcdc: lcdc@40008000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clock-names = "clcdclk", "apb_pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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