Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * NXP LPC1850 Clock Control Unit (CCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Each CGU base clock has several clock branches which can be turned on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) or off independently by the Clock Control Units CCU1 or CCU2. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) branch clocks are distributed between CCU1 and CCU2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - Above text taken from NXP LPC1850 User Manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) This binding uses the common clock binding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	Should be "nxp,lpc1850-ccu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	Shall define the base and range of the address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	containing clock control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #clock-cells:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	Shall have value <1>.  The permitted clock-specifier values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	are the branch clock names defined in table below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	Shall contain a list of phandles for the base clocks routed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	from the CGU to the specific CCU. See mapping of base clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	and CCU in table below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	Shall contain a list of names for the base clock routed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	from the CGU to the specific CCU. Valid CCU clock names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	"base_usb0_clk",  "base_periph_clk", "base_usb1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	"base_cpu_clk",   "base_spifi_clk",  "base_spi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	"base_apb1_clk",  "base_apb3_clk",   "base_adchs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	"base_sdio_clk",  "base_ssp0_clk",   "base_ssp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	"base_uart0_clk", "base_uart1_clk",  "base_uart2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	"base_uart3_clk", "base_audio_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Which branch clocks that are available on the CCU depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) specific LPC part. Check the user manual for your specific part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Example board file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	ccu1: clock-controller@40051000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		compatible = "nxp,lpc1850-ccu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		reg = <0x40051000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		clock-names = "base_apb3_clk",   "base_apb1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			      "base_spifi_clk",  "base_cpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			      "base_periph_clk", "base_usb0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			      "base_usb1_clk",   "base_spi_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	ccu2: clock-controller@40052000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		compatible = "nxp,lpc1850-ccu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		reg = <0x40052000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		clock-names = "base_audio_clk", "base_uart3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			      "base_uart2_clk", "base_uart1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			      "base_uart0_clk", "base_ssp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			      "base_ssp0_clk",  "base_sdio_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	/* A user of CCU brach clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	uart1: serial@40082000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };