Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Aisheng Dong <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   The Low-Power Clock Gate (LPCG) modules contain a local programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   model to control the clock gates for the peripherals. An LPCG module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   is used to locally gate the clocks for the associated peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   This level of clock gating is provided after the clocks are generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   by the SCU resources and clock controls. Thus even if the clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   enabled by these control bits, it might still not be running based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   on the base resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   ID in its "clocks" phandle cell. See the full list of clock IDs from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   include/dt-bindings/clock/imx8-clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)       - fsl,imx8qxp-lpcg-adma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)       - fsl,imx8qxp-lpcg-conn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)       - fsl,imx8qxp-lpcg-dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       - fsl,imx8qxp-lpcg-dsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)       - fsl,imx8qxp-lpcg-gpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)       - fsl,imx8qxp-lpcg-hsio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)       - fsl,imx8qxp-lpcg-img
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)       - fsl,imx8qxp-lpcg-lsio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)       - fsl,imx8qxp-lpcg-vpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)     const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)     #include <dt-bindings/clock/imx8-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)     #include <dt-bindings/firmware/imx/rsrc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)     clock-controller@5b200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)         compatible = "fsl,imx8qxp-lpcg-conn";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)         reg = <0x5b200000 0xb0000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)         #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)     mmc@5b010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)         reg = <0x5b010000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)         clock-names = "ipg", "per", "ahb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)         power-domains = <&pd IMX_SC_R_SDHC_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)     };