Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - A.s. Dong <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   i.MX7ULP Clock functions are under joint control of the System
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   modules, and Core Mode Controller (CMC)1 blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   The clocking scheme provides clear separation between M4 domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   and A7 domain. Except for a few clock sources shared between two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   domains, such as the System Oscillator clock, the Slow IRC (SIRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   and and the Fast IRC clock (FIRCLK), clock sources and clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   management are separated and contained within each domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   Note: this binding doc is only for A7 clock domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)   The System Clock Generation (SCG) is responsible for clock generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   and distribution across this device. Functions performed by the SCG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   include: clock reference selection, generation of clock used to derive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   processor, system, peripheral bus and external memory interface clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   source selection for peripheral clocks and control of power saving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   clock gating mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   ID in its "clocks" phandle cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   i.MX7ULP clock IDs of each module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)     const: fsl,imx7ulp-scg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)     const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)       - description: rtc osc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)       - description: system osc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)       - description: slow internal reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)       - description: fast internal reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)       - description: usb PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)       - const: rosc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)       - const: sosc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)       - const: sirc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)       - const: firc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)       - const: upll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)   - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)     #include <dt-bindings/clock/imx7ulp-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)     clock-controller@403e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)         compatible = "fsl,imx7ulp-scg1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)         reg = <0x403e0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)         clocks = <&rosc>, <&sosc>, <&sirc>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)                  <&firc>, <&upll>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)         clock-names = "rosc", "sosc", "sirc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)                       "firc", "upll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)         #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)     mmc@40380000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)         compatible = "fsl,imx7ulp-usdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)         reg = <0x40380000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)                  <&pcc2 IMX7ULP_CLK_USDHC1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)         clock-names ="ipg", "ahb", "per";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)         bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)     };