Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Clock bindings for Freescale i.MX6 SoloX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Anson Huang <Anson.Huang@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)     const: fsl,imx6sx-ccm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     description: CCM provides 2 interrupt requests, request 1 is to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       interrupt for frequency or mux change, request 2 is to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       interrupt for oscillator read or PLL lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)       - description: CCM interrupt request 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)       - description: CCM interrupt request 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       - description: 32k osc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)       - description: 24m osc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)       - description: ipp_di0 clock input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)       - description: ipp_di1 clock input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)       - description: anaclk1 clock input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)       - description: anaclk2 clock input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)       - const: ckil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)       - const: osc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)       - const: ipp_di0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)       - const: ipp_di1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)       - const: anaclk1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)       - const: anaclk2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)   - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)   # Clock Control Module node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)     clock-controller@20c4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)         compatible = "fsl,imx6sx-ccm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)         reg = <0x020c4000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)         #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)         clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)         clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)     };