Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/clock/imx5-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Clock bindings for Freescale i.MX5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Fabio Estevam <fabio.estevam@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   for the full list of i.MX5 clock IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)       - fsl,imx53-ccm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       - fsl,imx51-ccm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       - fsl,imx50-ccm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     description: CCM provides 2 interrupt requests, request 1 is to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)       interrupt for frequency or mux change, request 2 is to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)       interrupt for oscillator read or PLL lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       - description: CCM interrupt request 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)       - description: CCM interrupt request 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)     const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)     #include <dt-bindings/clock/imx5-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)     clock-controller@53fd4000{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)         compatible = "fsl,imx53-ccm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)         reg = <0x53fd4000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)         interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)                      <0 72 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)         #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)     can@53fc8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)         compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)         reg = <0x53fc8000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)         interrupts = <82>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)         clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)         clock-names = "ipg", "per";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)     };