^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Clock bindings for Freescale i.MX35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Steffen Trumtrar <s.trumtrar@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ID in its "clocks" phandle cell. The following is a full list of i.MX35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) clocks and IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Clock ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ckih 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) mpll 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ppll 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) mpll_075 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) arm 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) hsp 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) hsp_div 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) hsp_sel 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ahb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ipg 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) arm_per_div 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ahb_per_div 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ipg_per 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) uart_sel 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) uart_div 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) esdhc_sel 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) esdhc1_div 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) esdhc2_div 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) esdhc3_div 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) spdif_sel 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) spdif_div_pre 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spdif_div_post 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ssi_sel 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ssi1_div_pre 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ssi1_div_post 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ssi2_div_pre 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ssi2_div_post 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) usb_sel 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) usb_div 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) nfc_div 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) asrc_gate 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pata_gate 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) audmux_gate 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) can1_gate 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) can2_gate 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) cspi1_gate 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) cspi2_gate 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ect_gate 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) edio_gate 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) emi_gate 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) epit1_gate 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) epit2_gate 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) esai_gate 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) esdhc1_gate 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) esdhc2_gate 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) esdhc3_gate 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) fec_gate 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) gpio1_gate 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) gpio2_gate 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) gpio3_gate 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) gpt_gate 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) i2c1_gate 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) i2c2_gate 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) i2c3_gate 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) iomuxc_gate 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ipu_gate 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) kpp_gate 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mlb_gate 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mshc_gate 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) owire_gate 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pwm_gate 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) rngc_gate 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rtc_gate 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rtic_gate 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) scc_gate 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) sdma_gate 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spba_gate 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spdif_gate 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ssi1_gate 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ssi2_gate 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uart1_gate 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uart2_gate 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uart3_gate 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) usbotg_gate 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) wdog_gate 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) max_gate 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) admux_gate 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) csi_gate 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) csi_div 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) csi_sel 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) iim_gate 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) gpu2d_gate 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ckli_gate 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const: fsl,imx35-ccm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clock-controller@53f80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) compatible = "fsl,imx35-ccm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) reg = <0x53f80000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) interrupts = <31>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mmc@53fb4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) compatible = "fsl,imx35-esdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg = <0x53fb4000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) interrupts = <7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clocks = <&clks 9>, <&clks 8>, <&clks 43>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clock-names = "ipg", "ahb", "per";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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