^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/clock/imx31-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Clock bindings for Freescale i.MX31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Fabio Estevam <fabio.estevam@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ID in its "clocks" phandle cell. The following is a full list of i.MX31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) clocks and IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Clock ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) dummy 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ckih 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ckil 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) mpll 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) spll 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) upll 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) mcu_main 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) hsp 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ahb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) nfc 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ipg 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) per_div 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) per 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) csi_sel 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) fir_sel 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) csi_div 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) usb_div_pre 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) usb_div_post 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) fir_div_pre 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) fir_div_post 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) sdhc1_gate 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) sdhc2_gate 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) gpt_gate 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) epit1_gate 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) epit2_gate 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) iim_gate 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ata_gate 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) sdma_gate 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) cspi3_gate 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rng_gate 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) uart1_gate 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) uart2_gate 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ssi1_gate 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) i2c1_gate 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) i2c2_gate 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) i2c3_gate 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) hantro_gate 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mstick1_gate 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mstick2_gate 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) csi_gate 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rtc_gate 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) wdog_gate 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pwm_gate 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) sim_gate 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ect_gate 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) usb_gate 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) kpp_gate 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ipu_gate 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) uart3_gate 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) uart4_gate 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) uart5_gate 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) owire_gate 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ssi2_gate 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cspi1_gate 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cspi2_gate 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) gacc_gate 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) emi_gate 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rtic_gate 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) firi_gate 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const: fsl,imx31-ccm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) description: CCM provides 2 interrupt requests, request 1 is to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) interrupt for DVFS when a frequency change is requested, request 2 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) to generate interrupt for DPTC when a voltage change is requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - description: CCM DVFS interrupt request 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - description: CCM DPTC interrupt request 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clock-controller@53f80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) compatible = "fsl,imx31-ccm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg = <0x53f80000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) interrupts = <31>, <53>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) serial@43f90000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) compatible = "fsl,imx31-uart", "fsl,imx21-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg = <0x43f90000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) interrupts = <45>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clocks = <&clks 10>, <&clks 30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clock-names = "ipg", "per";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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