^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Clock bindings for Freescale i.MX28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Shawn Guo <shawnguo@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ID in its "clocks" phandle cell. The following is a full list of i.MX28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) clocks and IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Clock ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ref_xtal 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) pll0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) pll1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) pll2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ref_cpu 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ref_emi 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ref_io0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ref_io1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ref_pix 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ref_hsadc 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ref_gpmi 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) saif0_sel 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) saif1_sel 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) gpmi_sel 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ssp0_sel 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ssp1_sel 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ssp2_sel 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ssp3_sel 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) emi_sel 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) etm_sel 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) lcdif_sel 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) cpu 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ptp_sel 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) cpu_pll 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) cpu_xtal 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) hbus 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) xbus 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ssp0_div 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ssp1_div 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ssp2_div 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ssp3_div 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) gpmi_div 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) emi_pll 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) emi_xtal 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) lcdif_div 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) etm_div 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ptp 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) saif0_div 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) saif1_div 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk32k_div 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rtc 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) lradc 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) spdif_div 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk32k 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pwm 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) uart 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ssp0 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ssp1 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ssp2 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ssp3 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) gpmi 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spdif 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) emi 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) saif0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) saif1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) lcdif 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) etm 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) fec 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) can0 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) can1 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) usb0 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) usb1 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) usb0_phy 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) usb1_phy 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enet_out 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const: fsl,imx28-clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clock-controller@80040000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) compatible = "fsl,imx28-clkctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg = <0x80040000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) serial@8006a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) compatible = "fsl,imx28-auart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg = <0x8006a000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) interrupts = <112>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dmas = <&dma_apbx 8>, <&dma_apbx 9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clocks = <&clks 45>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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