^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/clock/imx23-clock.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Clock bindings for Freescale i.MX23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Shawn Guo <shawnguo@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The clock consumer should specify the desired clock by having the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ID in its "clocks" phandle cell. The following is a full list of i.MX23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) clocks and IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Clock ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ref_xtal 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) pll 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ref_cpu 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ref_emi 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ref_pix 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ref_io 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) saif_sel 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) lcdif_sel 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) gpmi_sel 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ssp_sel 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) emi_sel 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) cpu 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) etm_sel 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) cpu_pll 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) cpu_xtal 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) hbus 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) xbus 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) lcdif_div 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ssp_div 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) gpmi_div 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) emi_pll 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) emi_xtal 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) etm_div 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) saif_div 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) clk32k_div 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) rtc 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) adc 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) spdif_div 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) clk32k 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dri 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pwm 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) filt 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uart 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ssp 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) gpmi 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spdif 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) emi 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) saif 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) lcdif 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) etm 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) usb 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) usb_phy 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const: fsl,imx23-clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) '#clock-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - '#clock-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clock-controller@80040000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "fsl,imx23-clkctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg = <0x80040000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) serial@8006c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "fsl,imx23-auart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = <0x8006c000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) interrupts = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clocks = <&clks 32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dmas = <&dma_apbx 6>, <&dma_apbx 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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