Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * HiSilicon Clock and Reset Generator(CRG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The CRG module provides clock and reset signals to various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) modules within the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) This binding uses the following bindings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)     Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)     Documentation/devicetree/bindings/reset/reset.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - "hisilicon,hi3516cv300-crg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - "hisilicon,hi3516cv300-sysctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - "hisilicon,hi3519-crg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - "hisilicon,hi3798cv200-crg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   - "hisilicon,hi3798cv200-sysctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Each clock is assigned an identifier and client nodes use this identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) to specify the clock which they consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #reset-cells: should be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) A reset signal can be controlled by writing a bit register in the CRG module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) The reset specifier consists of two cells. The first cell represents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) register offset relative to the base address. The second cell represents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bit index in the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Example: CRG nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CRG: clock-reset-controller@12010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	compatible = "hisilicon,hi3519-crg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	reg = <0x12010000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	#reset-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Example: consumer nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) i2c0: i2c@12110000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	compatible = "hisilicon,hi3519-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	reg = <0x12110000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	clocks = <&CRG HI3519_I2C0_RST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	resets = <&CRG 0xe4 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };