Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Hisilicon Hi6220 Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Clock control registers reside in different Hi6220 system controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) please refer the following document to know more about the binding rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) for these system controllers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible: the compatible should be one of the following strings to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	indicate the clock controller functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	- "hisilicon,hi6220-acpu-sctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	- "hisilicon,hi6220-aoctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	- "hisilicon,hi6220-sysctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	- "hisilicon,hi6220-mediactrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	- "hisilicon,hi6220-pmctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	- "hisilicon,hi6220-stub-clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   the driver need use the sram to pass parameters for frequency change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - mboxes: use the label reference for the mailbox as the first parameter, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   second parameter is the channel number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	sys_ctrl: sys_ctrl@f7030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		compatible = "hisilicon,hi6220-sysctrl", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		reg = <0x0 0xf7030000 0x0 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Example 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	stub_clock: stub_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "hisilicon,hi6220-stub-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		hisilicon,hi6220-clk-sram = <&sram>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		mboxes = <&mailbox 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Each clock is assigned an identifier and client nodes use this identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) to specify the clock which they consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) All these identifier could be found in <dt-bindings/clock/hi6220-clock.h>.