Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Hisilicon Hi3670 Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Hi3670 clock controller generates and supplies clock to various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) controllers within the Hi3670 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: the compatible should be one of the following strings to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	indicate the clock controller functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	- "hisilicon,hi3670-crgctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	- "hisilicon,hi3670-pctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	- "hisilicon,hi3670-pmuctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	- "hisilicon,hi3670-sctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	- "hisilicon,hi3670-iomcu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	- "hisilicon,hi3670-media1-crg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	- "hisilicon,hi3670-media2-crg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Each clock is assigned an identifier and client nodes use this identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) to specify the clock which they consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	crg_ctrl: clock-controller@fff35000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		compatible = "hisilicon,hi3670-crgctrl", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		reg = <0x0 0xfff35000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	uart0: serial@fdf02000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "arm,pl011", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		reg = <0x0 0xfdf02000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			 <&crg_ctrl HI3670_PCLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		clock-names = "uartclk", "apb_pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	};