^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Samsung Exynos5433 CMU (Clock Management Units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Exynos5433 clock controller generates and supplies clock to various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) controllers within the Exynos5433 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) domains and bus clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) which generates clocks for LLI (Low Latency Interface) IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) which generates clocks for DRAM Memory Controller domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) which generates clocks for G2D/MDMA IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) which generates clocks for Cortex-A5/BUS/AUDIO clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) which generates global data buses clock and global peripheral buses clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) which generates clocks for 3D Graphics Engine IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) which generates clocks for GSCALER IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) which generates clocks for Cortex-A53 Quad-core processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) L2 cache controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) which generates clocks for MFC(Multi-Format Codec) IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - clocks: list of the clock controller input clock identifiers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) from common clock bindings. Please refer the next section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) to find the input clocks for a given controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - clock-names: list of the clock controller input clock names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) as described in clock-bindings.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Input clocks for top clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - sclk_mphy_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - sclk_mfc_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - sclk_bus_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) Input clocks for cpif clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Input clocks for mif clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) - sclk_mphy_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) Input clocks for fsys clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - sclk_ufs_mphy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - aclk_fsys_200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - sclk_pcie_100_fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - sclk_ufsunipro_fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - sclk_mmc2_fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - sclk_mmc1_fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - sclk_mmc0_fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - sclk_usbhost30_fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - sclk_usbdrd30_fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) Input clocks for g2d clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - aclk_g2d_266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - aclk_g2d_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) Input clocks for disp clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) - sclk_dsim1_disp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - sclk_dsim0_disp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - sclk_dsd_disp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - sclk_decon_tv_eclk_disp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - sclk_decon_vclk_disp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - sclk_decon_eclk_disp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - sclk_decon_tv_vclk_disp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - aclk_disp_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Input clocks for audio clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) - fout_aud_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Input clocks for bus0 clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) - aclk_bus0_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) Input clocks for bus1 clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) - aclk_bus1_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) Input clocks for bus2 clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) - aclk_bus2_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) Input clocks for g3d clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) - aclk_g3d_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) Input clocks for gscl clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) - aclk_gscl_111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) - aclk_gscl_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) Input clocks for apollo clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - sclk_bus_pll_apollo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) Input clocks for atlas clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) - sclk_bus_pll_atlas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) Input clocks for mscl clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) - sclk_jpeg_mscl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) - aclk_mscl_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) Input clocks for mfc clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) - aclk_mfc_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Input clocks for hevc clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) - aclk_hevc_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Input clocks for isp clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) - aclk_isp_dis_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) - aclk_isp_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) Input clocks for cam0 clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) - aclk_cam0_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) - aclk_cam0_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) - aclk_cam0_552
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) Input clocks for cam1 clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - sclk_isp_uart_cam1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) - sclk_isp_spi1_cam1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) - sclk_isp_spi0_cam1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) - aclk_cam1_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) - aclk_cam1_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) - aclk_cam1_552
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) Input clocks for imem clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) - oscclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) - aclk_imem_sssx_266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) - aclk_imem_266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) - aclk_imem_200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) - power-domains: a phandle to respective power domain node as described by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) generic PM domain bindings (see power/power_domain.txt for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) information).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) Each clock is assigned an identifier and client nodes can use this identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) to specify the clock which they consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) All available clocks are defined as preprocessor macros in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dt-bindings/clock/exynos5433.h header and can be used in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tree sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) Example 1: Examples of 'oscclk' source clock node are listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) xxti: xxti {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clock-output-names = "oscclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) Example 2: Examples of clock controller nodes are listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cmu_top: clock-controller@10030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) compatible = "samsung,exynos5433-cmu-top";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) reg = <0x10030000 0x0c04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "sclk_mphy_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "sclk_mfc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "sclk_bus_pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) <&cmu_cpif CLK_SCLK_MPHY_PLL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) <&cmu_mif CLK_SCLK_MFC_PLL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) <&cmu_mif CLK_SCLK_BUS_PLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cmu_cpif: clock-controller@10fc0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) compatible = "samsung,exynos5433-cmu-cpif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = <0x10fc0000 0x0c04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clock-names = "oscclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clocks = <&xxti>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) cmu_mif: clock-controller@105b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) compatible = "samsung,exynos5433-cmu-mif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg = <0x105b0000 0x100c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "sclk_mphy_pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) <&cmu_cpif CLK_SCLK_MPHY_PLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cmu_peric: clock-controller@14c80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) compatible = "samsung,exynos5433-cmu-peric";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg = <0x14c80000 0x0b08>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cmu_peris: clock-controller@10040000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) compatible = "samsung,exynos5433-cmu-peris";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg = <0x10040000 0x0b20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) cmu_fsys: clock-controller@156e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) compatible = "samsung,exynos5433-cmu-fsys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reg = <0x156e0000 0x0b04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "sclk_ufs_mphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "sclk_pcie_100_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "sclk_ufsunipro_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "sclk_mmc2_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "sclk_mmc1_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "sclk_mmc0_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "sclk_usbhost30_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "sclk_usbdrd30_fsys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) <&cmu_cpif CLK_SCLK_UFS_MPHY>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) <&cmu_top CLK_ACLK_FSYS_200>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) <&cmu_top CLK_SCLK_MMC2_FSYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) <&cmu_top CLK_SCLK_MMC1_FSYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) <&cmu_top CLK_SCLK_MMC0_FSYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cmu_g2d: clock-controller@12460000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) compatible = "samsung,exynos5433-cmu-g2d";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg = <0x12460000 0x0b08>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "aclk_g2d_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "aclk_g2d_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) <&cmu_top CLK_ACLK_G2D_266>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) <&cmu_top CLK_ACLK_G2D_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) power-domains = <&pd_g2d>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cmu_disp: clock-controller@13b90000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) compatible = "samsung,exynos5433-cmu-disp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) reg = <0x13b90000 0x0c04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "sclk_dsim1_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "sclk_dsim0_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "sclk_dsd_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "sclk_decon_tv_eclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "sclk_decon_vclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "sclk_decon_eclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "sclk_decon_tv_vclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "aclk_disp_333";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) <&cmu_mif CLK_SCLK_DSIM1_DISP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) <&cmu_mif CLK_SCLK_DSIM0_DISP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) <&cmu_mif CLK_SCLK_DSD_DISP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) <&cmu_mif CLK_ACLK_DISP_333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) power-domains = <&pd_disp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cmu_aud: clock-controller@114c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) compatible = "samsung,exynos5433-cmu-aud";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg = <0x114c0000 0x0b04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clock-names = "oscclk", "fout_aud_pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) power-domains = <&pd_aud>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cmu_bus0: clock-controller@13600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) compatible = "samsung,exynos5433-cmu-bus0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) reg = <0x13600000 0x0b04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) clock-names = "aclk_bus0_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clocks = <&cmu_top CLK_ACLK_BUS0_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) cmu_bus1: clock-controller@14800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) compatible = "samsung,exynos5433-cmu-bus1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) reg = <0x14800000 0x0b04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clock-names = "aclk_bus1_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clocks = <&cmu_top CLK_ACLK_BUS1_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) cmu_bus2: clock-controller@13400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) compatible = "samsung,exynos5433-cmu-bus2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) reg = <0x13400000 0x0b04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clock-names = "oscclk", "aclk_bus2_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cmu_g3d: clock-controller@14aa0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) compatible = "samsung,exynos5433-cmu-g3d";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reg = <0x14aa0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) clock-names = "oscclk", "aclk_g3d_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) power-domains = <&pd_g3d>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cmu_gscl: clock-controller@13cf0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) compatible = "samsung,exynos5433-cmu-gscl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg = <0x13cf0000 0x0b10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "aclk_gscl_111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "aclk_gscl_333";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) <&cmu_top CLK_ACLK_GSCL_111>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) <&cmu_top CLK_ACLK_GSCL_333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) power-domains = <&pd_gscl>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cmu_apollo: clock-controller@11900000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) compatible = "samsung,exynos5433-cmu-apollo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) reg = <0x11900000 0x1088>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) clock-names = "oscclk", "sclk_bus_pll_apollo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) cmu_atlas: clock-controller@11800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) compatible = "samsung,exynos5433-cmu-atlas";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) reg = <0x11800000 0x1088>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clock-names = "oscclk", "sclk_bus_pll_atlas";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) cmu_mscl: clock-controller@105d0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) compatible = "samsung,exynos5433-cmu-mscl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reg = <0x105d0000 0x0b10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "sclk_jpeg_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "aclk_mscl_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) <&cmu_top CLK_SCLK_JPEG_MSCL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) <&cmu_top CLK_ACLK_MSCL_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) power-domains = <&pd_mscl>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cmu_mfc: clock-controller@15280000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) compatible = "samsung,exynos5433-cmu-mfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) reg = <0x15280000 0x0b08>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clock-names = "oscclk", "aclk_mfc_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) power-domains = <&pd_mfc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cmu_hevc: clock-controller@14f80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) compatible = "samsung,exynos5433-cmu-hevc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) reg = <0x14f80000 0x0b08>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clock-names = "oscclk", "aclk_hevc_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) power-domains = <&pd_hevc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cmu_isp: clock-controller@146d0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) compatible = "samsung,exynos5433-cmu-isp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) reg = <0x146d0000 0x0b0c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "aclk_isp_dis_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "aclk_isp_400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) <&cmu_top CLK_ACLK_ISP_DIS_400>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) <&cmu_top CLK_ACLK_ISP_400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) power-domains = <&pd_isp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) cmu_cam0: clock-controller@120d0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) compatible = "samsung,exynos5433-cmu-cam0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) reg = <0x120d0000 0x0b0c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "aclk_cam0_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "aclk_cam0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "aclk_cam0_552";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) <&cmu_top CLK_ACLK_CAM0_333>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) <&cmu_top CLK_ACLK_CAM0_400>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) <&cmu_top CLK_ACLK_CAM0_552>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) power-domains = <&pd_cam0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cmu_cam1: clock-controller@145d0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) compatible = "samsung,exynos5433-cmu-cam1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reg = <0x145d0000 0x0b08>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "sclk_isp_uart_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "sclk_isp_spi1_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "sclk_isp_spi0_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "aclk_cam1_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "aclk_cam1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "aclk_cam1_552";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) <&cmu_top CLK_ACLK_CAM1_333>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) <&cmu_top CLK_ACLK_CAM1_400>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) <&cmu_top CLK_ACLK_CAM1_552>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) power-domains = <&pd_cam1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cmu_imem: clock-controller@11060000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) compatible = "samsung,exynos5433-cmu-imem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) reg = <0x11060000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clock-names = "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "aclk_imem_sssx_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "aclk_imem_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "aclk_imem_200";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) clocks = <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) <&cmu_top CLK_DIV_ACLK_IMEM_266>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) <&cmu_top CLK_DIV_ACLK_IMEM_200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) Example 3: UART controller node that consumes the clock generated by the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) serial_0: serial@14c10000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) compatible = "samsung,exynos5433-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) reg = <0x14C10000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) interrupts = <0 421 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) clocks = <&cmu_peric CLK_PCLK_UART0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) <&cmu_peric CLK_SCLK_UART0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) clock-names = "uart", "clk_uart_baud0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pinctrl-0 = <&uart0_bus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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