Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Samsung Exynos5420 Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Exynos5420 clock controller generates and supplies clock to various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Each clock is assigned an identifier and client nodes can use this identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) to specify the clock which they consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) All available clocks are defined as preprocessor macros in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) dt-bindings/clock/exynos5420.h header and can be used in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) tree sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Example 1: An example of a clock controller node is listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	clock: clock-controller@10010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		compatible = "samsung,exynos5420-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		reg = <0x10010000 0x30000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Example 2: UART controller node that consumes the clock generated by the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	   controller. Refer to the standard clock bindings for information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	   about 'clocks' and 'clock-names' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	serial@13820000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "samsung,exynos4210-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		reg = <0x13820000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		interrupts = <0 54 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		clock-names = "uart", "clk_uart_baud0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	};