Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Samsung Exynos5410 Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Exynos5410 clock controller generates and supplies clock to various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) controllers within the Exynos5410 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: should be "samsung,exynos5410-clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: should contain an entry specifying the root clock from external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   oscillator supplied through XXTI or XusbXTI pin.  This clock should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   defined using standard clock bindings with "fin_pll" clock-output-name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   That clock is being passed internally to the 9 PLLs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) All available clocks are defined as preprocessor macros in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) dt-bindings/clock/exynos5410.h header and can be used in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) tree sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Example 1: An example of a clock controller node is listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	fin_pll: xxti {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clock-frequency = <24000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clock-output-names = "fin_pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	clock: clock-controller@10010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		compatible = "samsung,exynos5410-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		reg = <0x10010000 0x30000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		clocks = <&fin_pll>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Example 2: UART controller node that consumes the clock generated by the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	   controller. Refer to the standard clock bindings for information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	   about 'clocks' and 'clock-names' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	serial@12c20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		compatible = "samsung,exynos4210-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		reg = <0x12C00000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		interrupts = <0 51 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		clock-names = "uart", "clk_uart_baud0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	};