^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Samsung Exynos5260 Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Exynos5260 has 13 clock controllers which are instantiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) independently from the device-tree. These clock controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) generate and supply clocks to various hardware blocks within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Each clock is assigned an identifier and client nodes can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) this identifier to specify the clock which they consume. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) available clocks are defined as preprocessor macros in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) dt-bindings/clock/exynos5260-clk.h header and can be used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) device tree sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) External clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) There are several clocks that are generated outside the SoC. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) is expected that they are defined using standard clock bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) with following clock-output-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - "fin_pll" - PLL input clock from XXTI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - "xrtcxti" - input clock from XRTCXTI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - "ioclk_pcm_extclk" - pcm external operation clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - "ioclk_spdif_extclk" - spdif external operation clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - "ioclk_i2s_cdclk" - i2s0 codec clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Phy clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) There are several clocks which are generated by specific PHYs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) These clocks are fed into the clock controller and then routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) the hardware blocks. These clocks are defined as fixed clocks in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) driver with following names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - "phyclk_dptx_phy_clk_div2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - "phyclk_mipi_dphy_4l_m_rxclkesc0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - "phyclk_usbhost20_phy_freeclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - "phyclk_usbhost20_phy_clk48mohci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - "phyclk_usbdrd30_udrd30_pipe_pclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Required Properties for Clock Controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 1) "samsung,exynos5260-clock-top"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 2) "samsung,exynos5260-clock-peri"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 3) "samsung,exynos5260-clock-egl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 4) "samsung,exynos5260-clock-kfc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 5) "samsung,exynos5260-clock-g2d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 6) "samsung,exynos5260-clock-mif"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 7) "samsung,exynos5260-clock-mfc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 8) "samsung,exynos5260-clock-g3d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 9) "samsung,exynos5260-clock-fsys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 10) "samsung,exynos5260-clock-aud"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 11) "samsung,exynos5260-clock-isp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 12) "samsung,exynos5260-clock-gscl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 13) "samsung,exynos5260-clock-disp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - reg: physical base address of the controller and the length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - clocks: list of clock identifiers which are fed as the input to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) the given clock controller. Please refer the next section to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) the input clocks for a given controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - clock-names: list of names of clocks which are fed as the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) to the given clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Input clocks for top clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - dout_mem_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - dout_bus_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - dout_media_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) Input clocks for peri clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - ioclk_pcm_extclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - ioclk_i2s_cdclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - ioclk_spdif_extclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - phyclk_hdmi_phy_ref_cko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - dout_aclk_peri_66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - dout_sclk_peri_uart0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - dout_sclk_peri_uart1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) - dout_sclk_peri_uart2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - dout_sclk_peri_spi0_b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - dout_sclk_peri_spi1_b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - dout_sclk_peri_spi2_b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - dout_aclk_peri_aud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - dout_sclk_peri_spi0_b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Input clocks for egl clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - dout_bus_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Input clocks for kfc clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - dout_media_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) Input clocks for g2d clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) - dout_aclk_g2d_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Input clocks for mif clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Input clocks for mfc clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) - dout_aclk_mfc_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) Input clocks for g3d clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) Input clocks for fsys clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) - phyclk_usbhost20_phy_phyclock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) - phyclk_usbhost20_phy_freeclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) - phyclk_usbhost20_phy_clk48mohci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) - phyclk_usbdrd30_udrd30_pipe_pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) - phyclk_usbdrd30_udrd30_phyclock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) - dout_aclk_fsys_200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) Input clocks for aud clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) - fout_aud_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - ioclk_i2s_cdclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) - ioclk_pcm_extclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Input clocks for isp clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) - dout_aclk_isp1_266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) - dout_aclk_isp1_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) - mout_aclk_isp1_266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Input clocks for gscl clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) - dout_aclk_gscl_400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) - dout_aclk_gscl_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) Input clocks for disp clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) - fin_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) - phyclk_dptx_phy_ch3_txd_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) - phyclk_dptx_phy_ch2_txd_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) - phyclk_dptx_phy_ch1_txd_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) - phyclk_dptx_phy_ch0_txd_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) - phyclk_hdmi_phy_tmds_clko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) - phyclk_hdmi_phy_ref_clko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) - phyclk_hdmi_phy_pixel_clko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) - phyclk_hdmi_link_o_tmds_clkhi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) - phyclk_mipi_dphy_4l_m_txbyte_clkhs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) - phyclk_dptx_phy_o_ref_clk_24m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) - phyclk_dptx_phy_clk_div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) - phyclk_mipi_dphy_4l_m_rxclkesc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) - phyclk_hdmi_phy_ref_cko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) - ioclk_spdif_extclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) - dout_aclk_peri_aud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - dout_aclk_disp_222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - dout_sclk_disp_pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) - dout_aclk_disp_333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) Example 1: An example of a clock controller node is listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clock_mfc: clock-controller@11090000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) compatible = "samsung,exynos5260-clock-mfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clock-names = "fin_pll", "dout_aclk_mfc_333";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg = <0x11090000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) Example 2: UART controller node that consumes the clock generated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) peri clock controller. Refer to the standard clock bindings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) information about 'clocks' and 'clock-names' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) serial@12c00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) compatible = "samsung,exynos4210-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) reg = <0x12C00000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) interrupts = <0 146 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clock-names = "uart", "clk_uart_baud0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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