^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Samsung Exynos4 Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Exynos4 clock controller generates and supplies clock to various controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) within the Exynos4 SoC. The clock binding described here is applicable to all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) SoC's in the Exynos4 family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Each clock is assigned an identifier and client nodes can use this identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) to specify the clock which they consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) All available clocks are defined as preprocessor macros in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) dt-bindings/clock/exynos4.h header and can be used in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) tree sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Example 1: An example of a clock controller node is listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) clock: clock-controller@10030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) compatible = "samsung,exynos4210-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) reg = <0x10030000 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example 2: UART controller node that consumes the clock generated by the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) controller. Refer to the standard clock bindings for information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) about 'clocks' and 'clock-names' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) serial@13820000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) compatible = "samsung,exynos4210-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) reg = <0x13820000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) interrupts = <0 54 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) clock-names = "uart", "clk_uart_baud0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) subsystem. Registers for those clocks are located in the ISP power domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Because those registers are also located in a different memory region than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) the main clock controller, a separate clock controller has to be defined for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) handling them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - compatible: should be "samsung,exynos4412-isp-clock".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - reg: physical base address of the ISP clock controller and length of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - clocks: list of the clock controller input clock identifiers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) from common clock bindings, should point to CLK_ACLK200 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CLK_ACLK400_MCUISP clocks from the main clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - clock-names: list of the clock controller input clock names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) as described in clock-bindings.txt, should be "aclk200" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "aclk400_mcuisp".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) - power-domains: a phandle to ISP power domain node as described by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) generic PM domain bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Example 3: The clock controllers bindings for Exynos4412 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clock: clock-controller@10030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) compatible = "samsung,exynos4412-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg = <0x10030000 0x18000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) isp_clock: clock-controller@10048000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) compatible = "samsung,exynos4412-isp-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg = <0x10048000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) power-domains = <&pd_isp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clock-names = "aclk200", "aclk400_mcuisp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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