Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Samsung Exynos3250 Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Exynos3250 clock controller generates and supplies clock to various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) controllers within the Exynos3250 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - "samsung,exynos3250-cmu-dmc" - controller compatible with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)     Exynos3250 SoC for Dynamic Memory Controller domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)      with Exynos3250 SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Each clock is assigned an identifier and client nodes can use this identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) to specify the clock which they consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) All available clocks are defined as preprocessor macros in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) dt-bindings/clock/exynos3250.h header and can be used in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) tree sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Example 1: Examples of clock controller nodes are listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	cmu: clock-controller@10030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		compatible = "samsung,exynos3250-cmu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		reg = <0x10030000 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	cmu_dmc: clock-controller@105c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		compatible = "samsung,exynos3250-cmu-dmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		reg = <0x105C0000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	cmu_isp: clock-controller@10048000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		compatible = "samsung,exynos3250-cmu-isp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		reg = <0x10048000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Example 2: UART controller node that consumes the clock generated by the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	   controller. Refer to the standard clock bindings for information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	   about 'clocks' and 'clock-names' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	serial@13800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		compatible = "samsung,exynos4210-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		reg = <0x13800000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		interrupts = <0 109 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		clock-names = "uart", "clk_uart_baud0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	};