Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) PLL divider based Dove clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) high speed clocks for a number of peripherals.  These dividers are part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) the PMU, and thus this node should be a child of the PMU node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) The following clocks are provided:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) ID	Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 0	AXI bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 1	GPU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 2	VMeta clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 3	LCD clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - compatible : shall be "marvell,dove-divider-clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - reg : shall be the register address of the Core PLL and Clock Divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)    Control 0 register.  This will cover that register, as well as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    Core PLL and Clock Divider Control 1 register.  Thus, it will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)    a size of 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - #clock-cells : from common clock binding; shall be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) divider_clk: core-clock@64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	compatible = "marvell,dove-divider-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	reg = <0x0064 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };