Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Samsung Audio Subsystem Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Samsung Audio Subsystem clock controller generates and supplies clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) to Audio Subsystem block available in the S5PV210 and compatible SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: should be "samsung,s5pv210-audss-clock".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: physical base address and length of the controller's register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - hclk: AHB bus clock of the Audio Subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)     not specified (i.e. xusbxti is used for PLL reference), it is fixed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     a clock named "xxti".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     specified, it is fixed to a clock named "iiscdclk0".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   - sclk_audio0: Audio bus clock, parent of mout_i2s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - clock-names: Aliases for the above clocks. They should be "hclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) All available clocks are defined as preprocessor macros in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) tree sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Example: Clock controller node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	clk_audss: clock-controller@c0900000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		compatible = "samsung,s5pv210-audss-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		reg = <0xc0900000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		clock-names = "hclk", "xxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 				"fout_epll", "sclk_audio0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		clocks = <&clocks DOUT_HCLKP>, <&xxti>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example: I2S controller node that consumes the clock generated by the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	 controller. Refer to the standard clock bindings for information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)          about 'clocks' and 'clock-names' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	i2s0: i2s@3830000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		/* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		clock-names = "iis", "i2s_opclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 				"i2s_opclk1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 				<&clk_audss CLK_DOUT_AUD_BUS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		/* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	};