^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Samsung Audio Subsystem Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Samsung Audio Subsystem clock controller generates and supplies clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) binding described here is applicable to all SoCs in Exynos family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg: physical base address and length of the controller's register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #clock-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) is used if not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) is used if not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - clock-names: Aliases for the above clocks. They should be "pll_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - power-domains: a phandle to respective power domain node as described by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) generic PM domain bindings (see power/power_domain.txt for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) information).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) The following is the list of clocks generated by the controller. Each clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) assigned an identifier and client nodes use this identifier to specify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) clock which they consume. Some of the clocks are available only on a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Exynos4 SoC and this is specified where applicable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Provided clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Clock ID SoC (if specific)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) -----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mout_audss 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mout_i2s 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dout_srp 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dout_aud_bus 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dout_i2s 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) srp_clk 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) i2s_bus 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) sclk_i2s 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pcm_bus 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) sclk_pcm 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) adma 10 Exynos5420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Example 1: An example of a clock controller node using the default input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clock names is listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clock_audss: audss-clock-controller@3810000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) compatible = "samsung,exynos5250-audss-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) reg = <0x03810000 0x0C>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Example 2: An example of a clock controller node with the input clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clock_audss: audss-clock-controller@3810000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "samsung,exynos5250-audss-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0x03810000 0x0C>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) <&ext_i2s_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Example 3: I2S controller node that consumes the clock generated by the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) controller. Refer to the standard clock bindings for information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) about 'clocks' and 'clock-names' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) i2s0: i2s@3830000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) compatible = "samsung,i2s-v5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = <0x03830000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dmas = <&pdma0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &pdma0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &pdma0 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dma-names = "tx", "rx", "tx-sec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clocks = <&clock_audss EXYNOS_I2S_BUS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <&clock_audss EXYNOS_I2S_BUS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) <&clock_audss EXYNOS_SCLK_I2S>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) <&clock_audss EXYNOS_MOUT_AUDSS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) <&clock_audss EXYNOS_MOUT_I2S>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "mout_audss", "mout_i2s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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