Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Binding for the AXS10X I2S PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding uses the common clock binding[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: shall be "snps,axs10x-i2s-pll-clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg : address and length of the I2S PLL register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks: shall be the input parent clock phandle for the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #clock-cells: from common clock binding; Should always be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	pll_clock: pll_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		clock-frequency = <27000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	i2s_clock@100a0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		compatible = "snps,axs10x-i2s-pll-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		reg = <0x100a0 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		clocks = <&pll_clock>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	};