Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Binding for the axi-clkgen clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding uses the common clock binding[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - #clock-cells : from common clock binding; Should always be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg : Address and length of the axi-clkgen register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks : Phandle and clock specifier for the parent clock(s). This must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	either reference one clock if only the first clock input is connected or two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	if both clock inputs are connected. For the later case the clock connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	to the first input must be specified first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clock-output-names : From common clock binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	clock@ff000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		compatible = "adi,axi-clkgen";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reg = <0xff000000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		clocks = <&osc 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	};