Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device Tree Clock bindings for arch-at91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding uses the common clock binding[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Slow Clock controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible : shall be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	"atmel,at91sam9x5-sckc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"atmel,sama5d3-sckc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"atmel,sama5d4-sckc" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	"microchip,sam9x60-sckc":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		at91 SCKC (Slow Clock Controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks : shall be the input parent clock phandle for the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   provided on XIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	sckc@fffffe50 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "atmel,at91sam9x5-sckc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		reg = <0xfffffe50 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clocks = <&slow_xtal>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Power Management Controller (PMC):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - compatible : shall be "atmel,<chip>-pmc", "syscon" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	"microchip,sam9x60-pmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	<chip> can be: at91rm9200, at91sam9260, at91sam9261,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	sama5d2, sama5d3 or sama5d4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - #clock-cells : from common clock binding; shall be set to 2. The first entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   is the type of the clock (core, system, peripheral or generated) and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   second entry its index as provided by the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - clocks : Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - clock-names: Must include the following entries: "slow_clk", "main_xtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   provided on XIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	pmc: pmc@f0018000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		compatible = "atmel,sama5d4-pmc", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		reg = <0xf0018000 0x120>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		#clock-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		clocks = <&clk32k>, <&main_xtal>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		clock-names = "slow_clk", "main_xtal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	};